Releases · stm32-rs/stm32-rs

04 Jul 20:02

adamgreig

v0.15.1

958ae32

v0.15.1 Latest

Latest

Updated to svd2rust 0.24.1 to fix critical codegen issue (#751)
Fix FSDEF field being marked read-only in SAI (#752)

What's Changed

Add PR #740 to changelog (oops!) by @adamgreig in #747
Set SAI FSDEF to read-write to match described usage, despite all the RMs calling it read-only by @adamgreig in #752
svd2rust: 0.24.0 -> 0.24.1 by @newAM in #751
Prepare for v0.15.1 release by @adamgreig in #753

Contributors

adamgreig and newAM

Assets 2

04 Jul 01:04

adamgreig

v0.15.0

19c9793

v0.15.0

Common changes:

Strip prefixes from many peripheral registers (#661)
Add SVDTOOLS env value for specifying patching tool (#673)
Fix HTML generation on macOS (#679)
Replace Python svd tools with Rust alternatives (#701)
Added missing TIMx:CR1:OPM, removed unused CNT_H, ARR_H, CCR_H (#684)
Use PascalCase for generated values of enums (#727)
Updated to svd2rust 0.24.0 (#733)
Document RTC ALARM and BKPR (#724)
Extensive internal refactor of GPIO patches (#717)
Change groupName of ADC_Common to ADC_Common (#719)
Fix field access on many SAI fields (#691)

Family-specific:

G0:
- G0B1/G0C1: Update SVDs (#666)
- G0B1/G0C1: Fix previous incorrect deletion of DMA1/2 (#675)
- Clear all vendor provided enumeratedValues (#686)
- Update SVDs, document DMA, various other patches (#687)
- Make FLASH_WRP??R and FLASH_SECR writeable (#690)
- G070: Rename SYSCFG_VREFBUF to SYSCFG, remove VREFBUF registers (#716)
- Fix DMA and TIM15 register field names (#695)
G4:
- Fix ADC ADSTP, ADSTART, ADDIS, ADEN bit enumerations (#699)
- Remove RNGSMEN -> RNGEN renaming to have AHB2SMENR.RNGSMEN (#729)
H7:
- h747: add midding DSI interrupt (#646)
- h735, h7b3: remove unavailable DSI peripheral (#648)
- Make ETH_MAC MMC mask register writable (#658)
- RM0455: Fix incorrect rename of OCTOSPI peripheral (#653)
- Arrayify HASH registers (#663)
- Add bit ranges to HDMI CRC registers (#671)
- H743/H753: Fix Overdrive and BDMADR fields (#649)
- h7b3: clear all enumeratedValues (#686)
- Change DMA CR to only cover SxCR, not LIFCR and HIFCR (#702)
- H735: Add TIM23 and TIM24 (#712)
- Fix ADC ADSTP, ADSTART, ADDIS, ADEN bit enumerations (#699)
- Arrayify HSEM registers (#735, #737)
- h747: add flash registers mirrored in bank2 (#704)
- H735: Add CORDIC and FMAC peripherals (#677)
- H735: Add missing TIM1, DCMI, OTG USB, RNG, LTDC, RAMECC interrupts (#677)
- Rename DBGSTBD1, DBGSTPD1, DBGSLPD1 fields to match RM (#677)
- RM0468: Add UART9/USART10, RM0455: fix USART base addresses (#652)
F0:
- F0x1/2/8: Add bit ranges to HDMI CRC registers (#671)
- Add missing CRC POL register (#710)
F2:
- Fix incorrect bit position for Ethernet MMCTIMR TGFM (#689)
- Add ADC EXTSEL enumerations (#707)
- Apply existing OTG_FSv1 fixes (#706)
F3:
- Add missing 'P' to JADST (#696)
- Fix ADC ADSTP, ADSTART, ADDIS, ADEN bit enumerations (#699)
- Fix various fields access (#734)
- F302: Rename DAC to DAC1 (#742)
F4:
- F469: Fix DSIHSOT_CCR register name (#664)
- Fix incorrect bit position for Ethernet MMCTIMR TGFM (#689)
- F411: Fix OTG_FS registers (#697)
- Add ADC EXTSEL enumerations (#707)
- Add GTPR register to UART (#713)
- Document TIM2 ITR1_RMP enums (#678)
- F410/411/412: add BDCR LSEMOD field (#708)
F7:
- Add SDMMC2EN and SDMMC2RST to F765, F7x7, F7x9 (#662)
- Fix incorrect bit position for Ethernet MMCTIMR TGFM (#689)
- Add bit ranges to HDMI CRC registers (#671)
- Add ADC EXTSEL enumerations (#707)
- Fix ADC DR RDATA name and description (#723)
- Document safe ranges for CNT/ARR/CCR (#700)
- Arrayify JPEG memory registers (#725)
L0:
- Re-add TIM21/TIM22 (#659)
- Fix various fields access (#734)
L4:
- Add documentation for FIREWALL (#660)
- Arrayify HASH registers (#663)
- L4R9: Fix DSIHSOT interrupt name (#664)
- L4R9: Add TIM3 and TIM4 (#669)
- L4x5/6/R9: Rename DBGMCU APB_FZR to remove underscores (#681)
- Add GPIOx ASCR and BRR registers (#680)
- Added missing channel 2 on TIM15 (#705)
- Fix ADC RDATA field name and description. (#723)
- Add more enums for clock selection registers (#720)
- Rename Polynomialcoefficients field to POL (#710)
- Remove COMP1/COMP2 prefix from field names, document fields (#682)
- Add L4R5 device (#740)
L5:
- Fix DMA CCR fields, arrayify GTZC VCTR (#715)
WB:
- Arrayify HSEM registers (#735, #737)
WL:
- Put all timers into common TIM group (#657)
- Fix various fields access (#734)
- Arrayify HSEM registers (#735, #737)

Contributors to this release:

@LeonSkoog @kenbell @ryan-summers @burrbull @richardeoin
@systec-ms @DerFetzer @newAM @jspngh @jamwaffles @sephamorr
@MathiasKoch @omion @davidlattimore @Sh3Rm4n @Windfisch @sorki
@taylorh140 @reitermarkus @larchuto @jonas-schievink @tim-seoss
@Wassasin @Gekkio @korken89 @maximeborges @sphw @dgoodland
@X-yl @disasm @Pagten @oldsheep68 @TomDeRybel @mattcarp12

What's Changed

Add missing DSI interrupt number for Stm32h747cm4 and Stm32h747cm7 by @LeonSkoog in #646
Remove DSI module from unsupported devices by @LeonSkoog in #648
wl5x / wle5: put all timers in TIM group by @kenbell in #657
Updating STM32H7 ETH_MAC MMC mask register writable by @ryan-summers in #658
strip prefixes ...

Contributors

dgoodlad, cpunion, and 34 other contributors

Assets 2

03 Oct 14:53

adamgreig

v0.14.0

1e0974f

v0.14.0

v0.14.0 2021-10-02

Family-specific:

F0:
- Fix duplicated aliased registers WAIT/AUTDLY and DMAEN/DMA1EN (#538)
F3:
- Mark HRTIM ISR FLT fields read-write (#592)
- Fix reset value for FLASH OBR (#600)
F4:
- Add FLASH and PLLR description for F446 (#533)
- Add FLTR register to all I2C peripherals (#534)
- Rename DSIHOST to DSI for F469 (#585)
- Fix UART RCC enable/reset bits (#589)
- Remove non-existant TIM8 from F401 (#633)
F7:
- Strip DSI prefix from DSI registers (#585)
- Fix reset value for RCC DCKCFGR (#600)
- Fix all timer registers (#606)
- Fix all SYSCFG registers (#612)
- Fix all RCC registers (#613)
- Fix all SDMMC registers (#620)
- Fix CRC INIT and POL register offsets (#632)
L0:
- Add L0x0 family (#505)
- Fix TIM CNT, ARR, CCR register sizes (#581)
- Fix RCC_CSR RMVF bit offset in L0x2 and L0x3 (#566)
L4:
- Fix ADC SQR1.L name and description (#519)
- Add missing APB1RSTR1.USBFSRST field for L4x3 (#526)
- Fix AHB1 CRC bits for L4x3 (#517)
- Add STM32L4R9 (#532)
- Add SPI register descriptions (#535)
- Strip DSI prefix from DSI registers (#585)
- Fix RTC registers in L41x and L42x (#580)
- Add USB_BCDR register, fix USB base address, and add USB interrupt (#580)
- Add CRSEN to APB1ENR1 (#580)
- Fix bit offset for CRC and USART bits in RCC (#571)
- Fix LCD RAM_COM register size and arrayify (#552)
L5:
- Fix TIM15 CCR2 address offset (#518)
H7:
- Add WWDG field descriptions (#502)
- Add DAC2AMEN to H7B3 (#500)
- Add LTDC field descriptions (#512)
- Fix FDCAN_TEST register to be writable (#574)
- Update to latest ST SVDs and add H72x/H73x devices (#554)
- Fix invalid patches to RCC registers (#615)
- Fix and cluster DFSDM registers (#637)
- Add SAI CR1 NOMCK alias bit to H743/753 and remove MCKEN (#640)
G0:
- Update to new ST SVD release (#514)
G4:
- Add I2C register definitions (#510)
- Add USB BCDR register (#506)
- Add GPIO register definitions (#531)
- Add more descriptions for RCC (#528)
WB:
- Enable in nightly releases (#509)
- Fix ADC SQR1.L name and description (#519)
- Add missing EXTI fields (#580)
- Fix TIM16 CR1 (#580)
- Rename ADC to ADC1, add new ADC_Common peripheral (#623)
- Fix SYSCFG register offsets (#624)
- Fixes for ADC, TIM16, and TIM17 (#625)
- Rename EXTI10_15 and EXTI5_9 interrupts to EXTI15_10 and EXTI9_5 (#634)
- Fix TIM2.CNT bit width (#635)
WL:
- Update to new ST SVD release (#507)
- Extensive patches and descriptions for WLE5, covering many peripherals (#559)
- Unify EXTI.IMRx for WLE5 to match dual-core parts (#590)
- Fix EXTI14 enumerated values (#599)
- Add register descriptions for dual-core variants (#628)
MP:
- Strip DSI prefix from DSI registers (#585)
- Add initial support for STM32MP153 device (#614)

Common:

Many devices using USART "v2" had write constraints fixed to allow 9-bit
words, affecting F0, F3, F7, H7, L0, L4, and WL families. (#558)
The rt feature is now enabled by default; use default-features=false to
disable (#582).
Updated to svd2rust 0.19, with changes to the generated crate API.
This update required a number of fixes to bugs in the SVD files,
especially including fixes to timers across all families (#540, #546, #596).
Fix a bug causing aliased registers to be suppressed in the HTML output
(#591)
Added a register map to HTML output (#598).
Allow generating HTML output for selected families only (#607).
Cortex-m-rt version 0.7 is now supported (#595, #603).