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expose Cr3::write_raw #445

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Jan 14, 2024
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expose Cr3::write_raw #445

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2 changes: 1 addition & 1 deletion src/registers/control.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -54,7 +54,7 @@
///
/// When a page fault occurs, the CPU sets this register to the faulting virtual address.
#[derive(Debug)]
pub struct Cr2;

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/// Contains the physical address of the highest-level page table.
#[derive(Debug)]
Expand Down Expand Up @@ -85,7 +85,7 @@
/// virtual-8086 mode.
const VIRTUAL_8086_MODE_EXTENSIONS = 1;
/// Enables support for protected-mode virtual interrupts.
const PROTECTED_MODE_VIRTUAL_INTERRUPTS = 1 << 1;

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/// When set, only privilege-level 0 can execute the `RDTSC` or `RDTSCP` instructions.
const TIMESTAMP_DISABLE = 1 << 2;
/// Enables I/O breakpoint capability and enforces treatment of `DR4` and `DR5` registers
Expand Down Expand Up @@ -181,7 +181,7 @@
asm!("mov {}, cr0", out(reg) value, options(nomem, nostack, preserves_flags));
}

value

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}

/// Write CR0 flags.
Expand Down Expand Up @@ -315,7 +315,7 @@
pub unsafe fn write_pcid(frame: PhysFrame, pcid: Pcid) {
unsafe {
Cr3::write_raw(frame, pcid.value());
}

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casting to the same type is unnecessary (`u16` -> `u16`)

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}

/// Write a new P4 table address into the CR3 register.
Expand All @@ -325,7 +325,7 @@
/// Changing the level 4 page table is unsafe, because it's possible to violate memory safety by
/// changing the page mapping.
#[inline]
unsafe fn write_raw(frame: PhysFrame, val: u16) {
pub unsafe fn write_raw(frame: PhysFrame, val: u16) {
let addr = frame.start_address();
let value = addr.as_u64() | val as u64;

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