Merge pull request #432 from xzmeng/fix-misc-doc-typos

Fix misc doc typos

Changelog.md

@@ -33,7 +33,7 @@
   - This trait is only available on nightly.
   - Gated behind `step_trait` feature flag
 - Add `UCet` and `SCet` registers ([#349](https://github.com/rust-osdev/x86_64/pull/349))
-- Use [`rustversion`](https://crates.io/crates/rustversion) to mark certian functions `const fn` on Rust 1.61 ([#353](https://github.com/rust-osdev/x86_64/pull/353))
+- Use [`rustversion`](https://crates.io/crates/rustversion) to mark certain functions `const fn` on Rust 1.61 ([#353](https://github.com/rust-osdev/x86_64/pull/353))
 - `Entry::handler_addr()` is now public ([#354](https://github.com/rust-osdev/x86_64/pull/354))
 - Increase packed structure alignment ([#362](https://github.com/rust-osdev/x86_64/pull/362))
 - Make more address methods `const fn` ([#369](https://github.com/rust-osdev/x86_64/pull/369))

src/instructions/interrupts.rs

@@ -109,10 +109,10 @@ where
 /// On some processors, the interrupt shadow of `sti` does not apply to
 /// non-maskable interrupts (NMIs). This means that an NMI can occur between
 /// the `sti` and `hlt` instruction, with the result that the CPU is put to
-/// sleep even though a new interrupt occured.
+/// sleep even though a new interrupt occurred.
 ///
 /// To work around this, it is recommended to check in the NMI handler if
-/// the interrupt occured between `sti` and `hlt` instructions. If this is the
+/// the interrupt occurred between `sti` and `hlt` instructions. If this is the
 /// case, the handler should increase the instruction pointer stored in the
 /// interrupt stack frame so that the `hlt` instruction is skipped.
 ///

src/registers/rflags.rs

@@ -28,7 +28,7 @@ bitflags! {
         const ALIGNMENT_CHECK = 1 << 18;
         /// Enable the virtual-8086 mode.
         const VIRTUAL_8086_MODE = 1 << 17;
-        /// Allows to restart an instruction following an instrucion breakpoint.
+        /// Allows to restart an instruction following an instruction breakpoint.
         const RESUME_FLAG = 1 << 16;
         /// Used by `iret` in hardware task switch mode to determine if current task is nested.
         const NESTED_TASK = 1 << 14;

src/structures/idt.rs

@@ -36,7 +36,7 @@ use volatile::Volatile;
 /// first entry, the entry for the `divide_error` exception. Note that the index access is
 /// not possible for entries for which an error code is pushed.
 ///
-/// The remaining entries are used for interrupts. They can be accesed through index
+/// The remaining entries are used for interrupts. They can be accessed through index
 /// operations on the idt, e.g. `idt[32]` returns the first interrupt entry, which is the 32nd IDT
 /// entry).
 ///
@@ -1271,7 +1271,7 @@ macro_rules! set_general_handler {
 #[macro_export]
 #[doc(hidden)]
 /// We can't loop in macros, but we can use recursion.
-/// This macro recursivly adds one more bit to it's arguments until we have 8 bits so that we can call set_general_handler_entry.
+/// This macro recursively adds one more bit to it's arguments until we have 8 bits so that we can call set_general_handler_entry.
 macro_rules! set_general_handler_recursive_bits {
     // if we have 8 all bits, construct the index from the bits, check if the entry is in range and invoke the macro that sets the handler
     ($idt:expr, $handler:ident, $range:expr, $bit7:tt, $bit6:tt, $bit5:tt, $bit4:tt, $bit3:tt, $bit2:tt, $bit1:tt, $bit0:tt) => {{
@@ -1282,7 +1282,7 @@ macro_rules! set_general_handler_recursive_bits {
             $crate::set_general_handler_entry!($idt, $handler, IDX, $bit7, $bit6, $bit5, $bit4, $bit3, $bit2, $bit1, $bit0);
         }
     }};
-    // otherwise recursivly invoke the macro adding one more bit
+    // otherwise recursively invoke the macro adding one more bit
     ($idt:expr, $handler:ident, $range:expr $(, $bits:tt)*) => {
         $crate::set_general_handler_recursive_bits!($idt, $handler, $range $(, $bits)*, 0);
         $crate::set_general_handler_recursive_bits!($idt, $handler, $range $(, $bits)*, 1);

src/structures/paging/mapper/mod.rs

@@ -60,7 +60,7 @@ pub enum TranslateResult {
     Mapped {
         /// The mapped frame.
         frame: MappedFrame,
-        /// The offset whithin the mapped frame.
+        /// The offset within the mapped frame.
         offset: u64,
         /// The entry flags in the lowest-level page table.
         ///
@@ -136,7 +136,7 @@ pub trait Mapper<S: PageSize> {
     ///   the same physical address. This is undefined behavior in Rust.
     ///     - This can be ensured by mapping each page to an individual physical
     ///       frame that is not mapped anywhere else.
-    /// - Creating uninitalized or invalid values: Rust requires that all values
+    /// - Creating uninitialized or invalid values: Rust requires that all values
     ///   have a correct memory layout. For example, a `bool` must be either a 0
     ///   or a 1 in memory, but not a 3 or 4. An exception is the `MaybeUninit`
     ///   wrapper type, which abstracts over possibly uninitialized memory.
@@ -224,7 +224,7 @@ pub trait Mapper<S: PageSize> {
     ///   the same physical address. This is undefined behavior in Rust.
     ///     - This can be ensured by mapping each page to an individual physical
     ///       frame that is not mapped anywhere else.
-    /// - Creating uninitalized or invalid values: Rust requires that all values
+    /// - Creating uninitialized or invalid values: Rust requires that all values
     ///   have a correct memory layout. For example, a `bool` must be either a 0
     ///   or a 1 in memory, but not a 3 or 4. An exception is the `MaybeUninit`
     ///   wrapper type, which abstracts over possibly uninitialized memory.

src/structures/paging/page.rs

@@ -357,7 +357,7 @@ pub struct PageRangeInclusive<S: PageSize = Size4KiB> {
 }
 
 impl<S: PageSize> PageRangeInclusive<S> {
-    /// Returns wether this range contains no pages.
+    /// Returns whether this range contains no pages.
     #[inline]
     pub fn is_empty(&self) -> bool {
         self.start > self.end