Merge branch 'rust-osdev:master' into enhancement/expose-cr3-write-raw

rust-osdev · Jan 14, 2024 · 83de2f3 · 83de2f3
2 parents c3eaa09 + 451ca2e
commit 83de2f3
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diff --git a/.github/dependabot.yml b/.github/dependabot.yml
@@ -0,0 +1,10 @@
+version: 2
+updates:
+  - package-ecosystem: github-actions
+    directory: "/"
+    schedule:
+      interval: weekly
+    ignore:
+      - dependency-name: "*"
+        update-types:
+          ["version-update:semver-minor", "version-update:semver-patch"]
diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
@@ -24,7 +24,7 @@ jobs:
           - 1.57
     runs-on: ubuntu-latest
     steps:
-      - uses: actions/checkout@v3
+      - uses: actions/checkout@v4
       - uses: actions-rs/toolchain@v1
         with:
           profile: minimal
@@ -76,7 +76,7 @@ jobs:
     timeout-minutes: 15
 
     steps:
-      - uses: actions/checkout@v3
+      - uses: actions/checkout@v4
       - uses: actions-rs/toolchain@v1
         with:
           profile: minimal
@@ -140,7 +140,7 @@ jobs:
 
     steps:
       - name: "Checkout Repository"
-        uses: actions/checkout@v3
+        uses: actions/checkout@v4
 
       - name: Cache binaries
         id: cache-bin
@@ -197,7 +197,7 @@ jobs:
     runs-on: ubuntu-latest
     timeout-minutes: 2
     steps:
-      - uses: actions/checkout@v3
+      - uses: actions/checkout@v4
       - uses: actions-rs/toolchain@v1
         with:
           toolchain: nightly
@@ -214,7 +214,7 @@ jobs:
     runs-on: ubuntu-latest
     timeout-minutes: 10
     steps:
-      - uses: actions/checkout@v3
+      - uses: actions/checkout@v4
       - uses: actions-rs/toolchain@v1
         with:
           toolchain: nightly
@@ -229,11 +229,11 @@ jobs:
     name: Semver Checks
     runs-on: ubuntu-latest
     steps:
-      - uses: actions/checkout@v3
+      - uses: actions/checkout@v4
       - uses: Swatinem/rust-cache@v2
         with:
           shared-key: "semver-checks"
           cache-targets: false
       - run: cargo install cargo-semver-checks --locked
       - name: Check semver
-        run: cargo semver-checks check-release
+        run: cargo +stable semver-checks check-release
diff --git a/.github/workflows/release.yml b/.github/workflows/release.yml
@@ -19,7 +19,7 @@ jobs:
 
     steps:
       - name: "Checkout Repository"
-        uses: actions/checkout@v3
+        uses: actions/checkout@v4
 
       # TODO: Remove when Python 3.11 is the default on the Gihtub Actions image
       - name: "Install Python 3.11"

diff --git a/Cargo.toml b/Cargo.toml
@@ -15,13 +15,13 @@ license = "MIT/Apache-2.0"
 name = "x86_64"
 readme = "README.md"
 repository = "https://github.com/rust-osdev/x86_64"
-version = "0.14.10"
+version = "0.14.11"
 edition = "2018"
 rust-version = "1.57" # Needed to support panic! in const fns
 
 [dependencies]
 bit_field = "0.10.1"
-bitflags = "1.3.2"
+bitflags = "2.3.2"
 volatile = "0.4.4"
 rustversion = "1.0.5"
 

diff --git a/Changelog.md b/Changelog.md
@@ -1,5 +1,38 @@
 # Unreleased
 
+## New Features
+
+- [Add `HandlerFuncType` trait](https://github.com/rust-osdev/x86_64/pull/439)
+
+# 0.14.11 – 2022-09-15
+
+## New Features
+
+- [Add missing IDT entries #CP and #HV`](https://github.com/rust-osdev/x86_64/pull/387)
+- [Adding next_higher_level to PageLevelIndex](https://github.com/rust-osdev/x86_64/pull/400)
+- [Adding `is_empty` to PageTable](https://github.com/rust-osdev/x86_64/pull/399)
+- [Add `Descriptor::tss_segment_unchecked`](https://github.com/rust-osdev/x86_64/pull/428)
+- [Add the `iretq` function to the `InterruptStackFrameValue` struct.](https://github.com/rust-osdev/x86_64/pull/431)
+- [add `flush_broadcast` and `tlbsync` functions](https://github.com/rust-osdev/x86_64/pull/403)
+
+## Fixes
+
+- [Change Star::write() to use checked subtractions](https://github.com/rust-osdev/x86_64/pull/422)
+- [add workaround for recursive page tables with recursive index 511](https://github.com/rust-osdev/x86_64/pull/425)
+- [Fix off-by-one in documentation](https://github.com/rust-osdev/x86_64/pull/427)
+- [Fix misc doc typos](https://github.com/rust-osdev/x86_64/pull/432)
+- [add compiler fences to enable and disable](https://github.com/rust-osdev/x86_64/pull/436)
+
+## Other Improvements
+
+- [set repr to transparent for various types](https://github.com/rust-osdev/x86_64/pull/402)
+- [Remove unused `doc_cfg` feature](https://github.com/rust-osdev/x86_64/pull/408)
+- [Enable `doc_auto_cfg` on `docs.rs` builds](https://github.com/rust-osdev/x86_64/pull/407)
+- [Add Descriptor::dpl const method and use it in GDT construction](https://github.com/rust-osdev/x86_64/pull/410)
+- [Bump bitflags to 2.3.2](https://github.com/rust-osdev/x86_64/pull/426)
+- [Add `inline` attribute to segment functions](https://github.com/rust-osdev/x86_64/pull/430)
+
+
 # 0.14.10 – 2022-07-10
 
 ## New Features
@@ -33,7 +66,7 @@
   - This trait is only available on nightly.
   - Gated behind `step_trait` feature flag
 - Add `UCet` and `SCet` registers ([#349](https://github.com/rust-osdev/x86_64/pull/349))
-- Use [`rustversion`](https://crates.io/crates/rustversion) to mark certian functions `const fn` on Rust 1.61 ([#353](https://github.com/rust-osdev/x86_64/pull/353))
+- Use [`rustversion`](https://crates.io/crates/rustversion) to mark certain functions `const fn` on Rust 1.61 ([#353](https://github.com/rust-osdev/x86_64/pull/353))
 - `Entry::handler_addr()` is now public ([#354](https://github.com/rust-osdev/x86_64/pull/354))
 - Increase packed structure alignment ([#362](https://github.com/rust-osdev/x86_64/pull/362))
 - Make more address methods `const fn` ([#369](https://github.com/rust-osdev/x86_64/pull/369))

diff --git a/src/addr.rs b/src/addr.rs
@@ -1,6 +1,5 @@
 //! Physical and virtual addresses manipulation
 
-#[cfg(feature = "step_trait")]
 use core::convert::TryFrom;
 use core::fmt;
 #[cfg(feature = "step_trait")]
@@ -11,7 +10,6 @@ use crate::structures::paging::page_table::PageTableLevel;
 use crate::structures::paging::{PageOffset, PageTableIndex};
 use bit_field::BitField;
 
-#[cfg(feature = "step_trait")]
 const ADDRESS_SPACE_SIZE: u64 = 0x1_0000_0000_0000;
 
 /// A canonical 64-bit virtual memory address.
@@ -131,8 +129,8 @@ impl VirtAddr {
     // doesn't truncate.
     #[cfg(any(target_pointer_width = "32", target_pointer_width = "64"))]
     #[inline]
-    pub fn from_ptr<T>(ptr: *const T) -> Self {
-        Self::new(ptr as u64)
+    pub fn from_ptr<T: ?Sized>(ptr: *const T) -> Self {
+        Self::new(ptr as *const () as u64)
     }
 
     /// Converts the address to a raw pointer.
@@ -226,6 +224,42 @@ impl VirtAddr {
     pub const fn page_table_index(self, level: PageTableLevel) -> PageTableIndex {
         PageTableIndex::new_truncate((self.0 >> 12 >> ((level as u8 - 1) * 9)) as u16)
     }
+
+    // FIXME: Move this into the `Step` impl, once `Step` is stabilized.
+    pub(crate) fn steps_between_impl(start: &Self, end: &Self) -> Option<usize> {
+        let mut steps = end.0.checked_sub(start.0)?;
+
+        // Check if we jumped the gap.
+        if end.0.get_bit(47) && !start.0.get_bit(47) {
+            steps = steps.checked_sub(0xffff_0000_0000_0000).unwrap();
+        }
+
+        usize::try_from(steps).ok()
+    }
+
+    // FIXME: Move this into the `Step` impl, once `Step` is stabilized.
+    pub(crate) fn forward_checked_impl(start: Self, count: usize) -> Option<Self> {
+        let offset = u64::try_from(count).ok()?;
+        if offset > ADDRESS_SPACE_SIZE {
+            return None;
+        }
+
+        let mut addr = start.0.checked_add(offset)?;
+
+        match addr.get_bits(47..) {
+            0x1 => {
+                // Jump the gap by sign extending the 47th bit.
+                addr.set_bits(47.., 0x1ffff);
+            }
+            0x2 => {
+                // Address overflow
+                return None;
+            }
+            _ => {}
+        }
+
+        Some(Self::new(addr))
+    }
 }
 
 impl fmt::Debug for VirtAddr {
@@ -346,37 +380,11 @@ impl Sub<VirtAddr> for VirtAddr {
 #[cfg(feature = "step_trait")]
 impl Step for VirtAddr {
     fn steps_between(start: &Self, end: &Self) -> Option<usize> {
-        let mut steps = end.0.checked_sub(start.0)?;
-
-        // Check if we jumped the gap.
-        if end.0.get_bit(47) && !start.0.get_bit(47) {
-            steps = steps.checked_sub(0xffff_0000_0000_0000).unwrap();
-        }
-
-        usize::try_from(steps).ok()
+        Self::steps_between_impl(start, end)
     }
 
     fn forward_checked(start: Self, count: usize) -> Option<Self> {
-        let offset = u64::try_from(count).ok()?;
-        if offset > ADDRESS_SPACE_SIZE {
-            return None;
-        }
-
-        let mut addr = start.0.checked_add(offset)?;
-
-        match addr.get_bits(47..) {
-            0x1 => {
-                // Jump the gap by sign extending the 47th bit.
-                addr.set_bits(47.., 0x1ffff);
-            }
-            0x2 => {
-                // Address overflow
-                return None;
-            }
-            _ => {}
-        }
-
-        Some(Self::new(addr))
+        Self::forward_checked_impl(start, count)
     }
 
     fn backward_checked(start: Self, count: usize) -> Option<Self> {
@@ -836,4 +844,11 @@ mod tests {
     fn test_phys_addr_align_up_overflow() {
         PhysAddr::new(0x000f_ffff_ffff_ffff).align_up(2u64);
     }
+
+    #[test]
+    fn test_from_ptr_array() {
+        let slice = &[1, 2, 3, 4, 5];
+        // Make sure that from_ptr(slice) is the address of the first element
+        assert_eq!(VirtAddr::from_ptr(slice), VirtAddr::from_ptr(&slice[0]));
+    }
 }
diff --git a/src/instructions/interrupts.rs b/src/instructions/interrupts.rs
@@ -15,8 +15,10 @@ pub fn are_enabled() -> bool {
 /// This is a wrapper around the `sti` instruction.
 #[inline]
 pub fn enable() {
+    // Omit `nomem` to imitate a lock release. Otherwise, the compiler
+    // is free to move reads and writes through this asm block.
     unsafe {
-        asm!("sti", options(nomem, nostack));
+        asm!("sti", options(preserves_flags, nostack));
     }
 }
 
@@ -25,8 +27,10 @@ pub fn enable() {
 /// This is a wrapper around the `cli` instruction.
 #[inline]
 pub fn disable() {
+    // Omit `nomem` to imitate a lock acquire. Otherwise, the compiler
+    // is free to move reads and writes through this asm block.
     unsafe {
-        asm!("cli", options(nomem, nostack));
+        asm!("cli", options(preserves_flags, nostack));
     }
 }
 
@@ -109,10 +113,10 @@ where
 /// On some processors, the interrupt shadow of `sti` does not apply to
 /// non-maskable interrupts (NMIs). This means that an NMI can occur between
 /// the `sti` and `hlt` instruction, with the result that the CPU is put to
-/// sleep even though a new interrupt occured.
+/// sleep even though a new interrupt occurred.
 ///
 /// To work around this, it is recommended to check in the NMI handler if
-/// the interrupt occured between `sti` and `hlt` instructions. If this is the
+/// the interrupt occurred between `sti` and `hlt` instructions. If this is the
 /// case, the handler should increase the instruction pointer stored in the
 /// interrupt stack frame so that the `hlt` instruction is skipped.
 ///

diff --git a/src/instructions/segmentation.rs b/src/instructions/segmentation.rs
@@ -10,6 +10,7 @@ use core::arch::asm;
 
 macro_rules! get_reg_impl {
     ($name:literal) => {
+        #[inline]
         fn get_reg() -> SegmentSelector {
             let segment: u16;
             unsafe {
@@ -25,6 +26,7 @@ macro_rules! segment_impl {
         impl Segment for $type {
             get_reg_impl!($name);
 
+            #[inline]
             unsafe fn set_reg(sel: SegmentSelector) {
                 unsafe {
                     asm!(concat!("mov ", $name, ", {0:x}"), in(reg) sel.0, options(nostack, preserves_flags));
@@ -38,6 +40,7 @@ macro_rules! segment64_impl {
     ($type:ty, $name:literal, $base:ty) => {
         impl Segment64 for $type {
             const BASE: Msr = <$base>::MSR;
+            #[inline]
             fn read_base() -> VirtAddr {
                 unsafe {
                     let val: u64;
@@ -46,6 +49,7 @@ macro_rules! segment64_impl {
                 }
             }
 
+            #[inline]
             unsafe fn write_base(base: VirtAddr) {
                 unsafe{
                     asm!(concat!("wr", $name, "base {}"), in(reg) base.as_u64(), options(nostack, preserves_flags));
@@ -66,6 +70,7 @@ impl Segment for CS {
     /// Note we cannot use a "far call" (`lcall`) or "far jmp" (`ljmp`) to do this because then we
     /// would only be able to jump to 32-bit instruction pointers. Only Intel implements support
     /// for 64-bit far calls/jumps in long-mode, AMD does not.
+    #[inline]
     unsafe fn set_reg(sel: SegmentSelector) {
         unsafe {
             asm!(
@@ -97,6 +102,7 @@ impl GS {
     ///
     /// This function is unsafe because the caller must ensure that the
     /// swap operation cannot lead to undefined behavior.
+    #[inline]
     pub unsafe fn swap() {
         unsafe {
             asm!("swapgs", options(nostack, preserves_flags));