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An out-of-order processor that supports multiple instruction sets.

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losfair/MagiCore

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MagiCore

An out-of-order processor that supports multiple instruction sets. My playground for experimenting with new microarchitecture & ISA ideas.

Architecture

ISA support status

  • RISC-V RV32IMAU
  • RISC-V RV64IMAU
  • eBPF
  • MIPS

Performance

Currently MagiCore's frontend (IFetch/Decode) is not superscalar so the performance is limited to <1 IPC. 2.27 CoreMark/MHz, ~106MHz on Artix 7.