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A finite state machine for a T-section traffic light controller

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Traffic Light Controller (FSM)

Contents

Case Studies

T-Section Road

In this case we will be studying a T-section road, where there will be a main road with 2 lanes, and a side road joining it.

In this road there will be four turns that will be requiring the assistance of a traffic light, they are:

Turn Detail
M1 Crossing T-section of main road from left lane.
MT Car turns from main left lane to side road.
M2 Car Crossing the T-section from right lane
S Car Joining from side road to main road

So will have six states, it will go through them one by one after their respective durations.

In the demo, only the durations for states S1, S3 and S5 are set. For states S2, S4 and S6, which are essentially a yellow-light state, the duration is defaulted to 2 secs

Installation

Make sure you have pipenv installed, then run following commands in the project directory.

  1. Install dependencies
    pipenv sync
  2. Run the project
    pipenv run python main.py

References

  1. https://en.wikipedia.org/wiki/Traffic_light_control_and_coordination
  2. https://www.fpga4student.com/2016/11/verilog-code-for-traffic-light-system.html
  3. https://www.watelectronics.com/how-traffic-light-control-system-works/
  4. https://www.researchgate.net/publication/305674408_Smart_traffic_light_control_system

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