Releases: cvut/qtrvsim
QtRvSim version 0.9.7 release
- GUI: fix examples button crashes on Windows and sometimes other platforms
- GUI: fix crash when no tab is selected
- CI: add windows libs to artifacts and use more cores available
- CI: Make pack QT with Win artifact
- Project: Use the include directory for LibElf on macOS, Homebrew misses RISC-V
- Machine: set SXL and UXL to 64-bit XLEN for RV64
- Students work was funded by RPAPS 2023 initiative at Czech Technical University in Prague Faculty of Electrical Engineering, https://fel.cvut.cz/
- We thanks for actual funding to Czech Technical University https://www.cvut.cz/
For Ubuntu use https://launchpad.net/~qtrvsimteam/+archive/ubuntu/ppa
For SUSE, Fedora and Debian https://software.opensuse.org/download.html?project=home%3Ajdupak&package=qtrvsim
For Arch https://aur.archlinux.org/pkgbase/qtrvsim
WebAssembly online version https://comparch.edu.cvut.cz/qtrvsim/app
QtRvSim articles, presentations and their recordings as well as more about Computer Architectures courses at the Czech Technical University in Prague are presented at https://comparch.edu.cvut.cz/
The educational VHDL RISC-V core modeled according to the QtRvSim (single cycle and 5-stage pipeline) has been designed by Damir Gruncl for the CTU FEE Advanced Computer Architectures course https://gitlab.fel.cvut.cz/b4m35pap/rvapo-vhdl and tested in GHDL simulation and on Zilinx Zynq and iCE-40 FPGA targets
QtRvSim version 0.9.6 release
- GUI: add reset widows menu entry to restore default windows layout
- Machine: extend CSR support to pass rv32mi-p-mcsr and rv64mi-p-mcsr official test
- Machine: serial port interrupts reworked for RISC-V as platform irq 16 and 17
- GUI: RISC-V ACLINT MTIMER mapping added into resources/samples/template.S
- Machine: implemented RISC-V A extension for RV32IMA/RV64IMA support
- GUI: the XLEN, atomic and multiply options available in new simulation dialog
- GUI: update registers and CSR views for bare RV64IMA support
- Machine and GUI: simple level 2 cache implementation
- GUI: increase cache set count limit to 1024
- CLI: add isa-variant, cycle-limit and l2-cache options
- CLI: dump-ranges allows to use symbols even from internal assembly
- Memory: correctly propagate external/DMA changes to GUI
- Machine: where possible, re-implement pseudo instructions by aliase tables
- os_emulation: resolve problem with write and read from/to stack area on RV32
- GUI: fix double free of children widgets in control register widget
- GUI: refactor gui source file to tree structure
- GUI: program view - collapse address and breakpoint if space is limited
- GUI: split central widget tabs to coreview and editor
- GUI: editor line numbers and highlight error in the editor on message click
- GUI: editor toggle comment (ctrl+/)
- GUI: ensure that all lines of external make process output are processed
- os_emulation: correct ftruncate syscall arguments for 64 and 32-bit ABI
- Update README.md to document interrupt, trap, ACLINT+MTIMER and AMO support
- CI: drop support for Ubuntu 18
- Project: bump to c++17
- Students work was funded by RPAPS 2023 initiative at Czech Technical University in Prague Faculty of Electrical Engineering, https://fel.cvut.cz/
- We thanks for actual funding to Czech Technical University https://www.cvut.cz/
For Ubuntu use https://launchpad.net/~qtrvsimteam/+archive/ubuntu/ppa
For SUSE, Fedora and Debian https://software.opensuse.org/download.html?project=home%3Ajdupak&package=qtrvsim
For Arch https://aur.archlinux.org/pkgbase/qtrvsim
WebAssembly online version https://comparch.edu.cvut.cz/qtrvsim/app
QtRvSim articles, presentations and their recordings as well as more about Computer Architectures courses at the Czech Technical University in Prague are presented at https://comparch.edu.cvut.cz/
The project has been presented on FOSDEM 2023, presentation and recordings are available
- QtRVSim—Education from Assembly to Pipeline, Cache Performance, and C Level Programming
- https://archive.fosdem.org/2023/schedule/event/rv_qtrvsim/
The educational VHDL RISC-V core modeled according to the QtRvSim (single cycle and 5-stage pipeline) has been designed by Damir Gruncl for the CTU FEE Advanced Computer Architectures course https://gitlab.fel.cvut.cz/b4m35pap/rvapo-vhdl and tested in GHDL simulation and on Zilinx Zynq and iCE-40 FPGA targets
QtRVSim version 0.9.5 release
- Machine: use cvector in instruction args to spedup decoding
- Machine: move controlstate to csr and prepare BitArg to be usd there
- Machine: use method for CSR writes to enable mutual register dependencies
- Machine: CSR: define mie register.
- Machine: CSR: fix conditions for register write and add mie to the list.
- Machine: fix range for branch instructions B-encoding
- CLI: add simple tracer for memory reads and writes.
- CLI: initial support to enable OS emulation even for CLI version
- GUI: update coreview graphics by Michal Stepanosvky
- GUI: fix wrong svg label connection and reset all to zero
- Students work was funded by RPAPS 2022 initiative at Czech Technical University in Prague Faculty of Electrical Engineering, https://fel.cvut.cz/
- We thanks for actual funding to Czech Technical University https://www.cvut.cz/
For Ubuntu use https://launchpad.net/~qtrvsimteam/+archive/ubuntu/ppa
For SUSE, Fedora and Debian https://software.opensuse.org/download.html?project=home%3Ajdupak&package=qtrvsim
For Arch https://aur.archlinux.org/pkgbase/qtrvsim
Emscripten online version https://comparch.edu.cvut.cz/qtrvsim/app
QtRvSim articles, presentations and their recordings as well as more about Computer Architectures courses at the Czech Technical University in Prague are presented at https://comparch.edu.cvut.cz/
FOSDEM 2023 RISC-V devroom is the next chance for in-face meeting. The presentation
QtRVSim—Education from Assembly to Pipeline, Cache Performance, and C Level Programming
https://fosdem.org/2023/schedule/event/rv_qtrvsim/
is scheduled on Sunday February 5 at 09:40 CET (UTC + 1). Streaming will be available as well.
The RISCV.otg Academic and Training SIG online meeting on Thursday 19 at 8 AM Pacific (5 PM CEST) is another event where QtRvSim together with our materials for education will be presented together with hands-on session.
QtRVSim version 0.9.4 release
- GUI: Async modal library to overcome WebAssembly/Emscripten limitations
- Wasm: support and build improved
- os_emulation: correct open flags O_xxx values to match RISC-V Linux ABI.
- packaging: fix Fedora build according to Jan Grulich advice.
- README.md: add reference to Embedded World Conference 2022 article.
- qtrvsim_tester: Tomas Veznik implemented testing against official RISC/V ISA tests.
- CI: speedup by using common build of official tests
- Machine: initial support for CSR instructions by Jakub Dupak
- GUI: CSR: syntax highlight CSR reg names
- Machine: CSR: disassemble CSR register based on the mnemonic register settings
- GUI: save mnemonic registers settings
- Machine: add support for 64-bit RV64IM target and related 32-bit/word limited instructions
- README.md: update information about basic 64-bit support.
- Students work was funded by RPAPS 2022 initiative at Czech Technical University in Prague Faculty of Electrical Engineering, https://fel.cvut.cz/
- We thanks for actual funding to Czech Technical University https://www.cvut.cz/
For Ubuntu use https://launchpad.net/~qtrvsimteam/+archive/ubuntu/ppa
For SUSE, Fedora and Debian https://software.opensuse.org/download.html?project=home%3Ajdupak&package=qtrvsim
For Arch https://aur.archlinux.org/pkgbase/qtrvsim
Experimental Emscripten build can be accessed online https://comparch.edu.cvut.cz/qtrvsim/app
QtRvSim has been presented at Embedded World Conference 2022 in Session 10.3 – System-on-Chip (SoC) Design RISC-V Development https://events.weka-fachmedien.de/embedded-world-conference/
The presentation slides and related article QtRvSim – RISC-V Simulator for Computer Architectures Classes can be found on Computer Architectures courses materials page of the Czech Technical University in Prague https://comparch.edu.cvut.cz/
Upcoming presentation with live stream at DevConf CZ MINI https://www.devconf.info/cz/
QtRVSim – RISC-V Simulator for Computer Architectures Classes talk is scheduled on Thursday, November 3, 17:30 CET (16:30 UTC).
QtRVSim version 0.9.3 release
- Debian package updated to version 0.9.3.
- Machine: fix LCD display endianness.
- Machine: correct memory stall cycles computation.
- Machine: correct unaligned and partial (lb, sb, lh, sh) to peripheral registers.
- Packaging: flatpak support kindly provided by David Heidelberg david@ixit.cz
- Machine and GUI: switch to RISC-V CSR names and remove references to MIPS COP0.
- Machine: correct parsing of registers s10 and s11 names.
- Machine: fix null pointer usage in cache
- GUI: fix null pointer usage in cache
- Machine: correct cache graphics visualization for byte accesses.
- Machine: LFU cache policy incorrect use of sets count instead of degree of associativity.
- Students work was funded by RPAPS 2021 initiative at Czech Technical University in Prague Faculty of Electrical Engineering, https://fel.cvut.cz/
- We thanks for actual funding from followup project by Czech Technical University https://www.cvut.cz/
For Ubuntu use https://launchpad.net/~qtrvsimteam/+archive/ubuntu/ppa
For Arch, SUSE, Fedora and Debian https://software.opensuse.org/download.html?project=home%3Ajdupak&package=qtrvsim
Experimental Emscripten build can be accessed online https://comparch.edu.cvut.cz/qtrvsim/app
QtRvSim has been presented at Embedded World Conference 2022 in Session 10.3 – System-on-Chip (SoC) Design RISC-V Development https://events.weka-fachmedien.de/embedded-world-conference/program/
The presentation slides and related article QtRvSim – RISC-V Simulator for Computer Architectures Classes can be found on Computer Architectures courses materials page of the Czech Technical University in Prague https://comparch.edu.cvut.cz/
QtRVSim version 0.9.2 release
- GUI: rework of coreview graphics to correspond to Mr. Stepanovsky slides (Jakub Dupak)
- CI: downgrade runner os to win2019 to prevent failing builds (Jakub Dupak)
- WASM: fix exception support (Jakub Dupak)
- LRU cache policy fix (check was incoorect only for flush, i.e. fence instruction)
- Machine: basic RV32M support (no specific GUI provided, considered as part of ALU) (Jakub Dupak)
- README.md update, document RV32M support (Jakub Dupak)
- Machine: RISC-V ABI places stack pointer into x2 register. (Pavel Pisa)
- Machine: rewrite all core_alu_forward and complex memory tests for RISC-V (Pavel Pisa)
- Machine: RISC-V is by default little endian, even when ELF file is not loaded (Pavel Pisa)
- The original QtMips project https://github.com/cvut/QtMips
- Students work was funded by RPAPS 2021 initiative at Czech Technical University in Prague Faculty of Electrical Engineering, https://fel.cvut.cz/
- We thanks for actual funding from followup project by Czech Technical University https://www.cvut.cz/
For Ubuntu use https://launchpad.net/~qtrvsimteam/+archive/ubuntu/ppa
For Arch, SUSE, Fedora and Debian https://software.opensuse.org/download.html?project=home%3Ajdupak&package=qtrvsim
Experimental Emscripten build can be accessed online https://dev.jakubdupak.com/qtrvsim/
QtRVSim version 0.9.1 release
- QtRVSim incremental update after use on the first lecture and seminaries with CTU students.
- The original QtMips project https://github.com/cvut/QtMips
- The memory model, visualization and packaging updated by Jakub Dupak
- The initial limited RV32 instruction set subset has been initiated by Max Hollmann
- The CPU diagram is slowly updated to match version prepared by Michal Stepanovsky
- Project coordination Pavel Pisa
- Students work was funded by RPAPS 2021 initiative at Czech Technical University in Prague Faculty of Electrical Engineering, https://fel.cvut.cz/
- We thanks for actual funding from followup project by Czech Technical University https://www.cvut.cz/
For Ubuntu use https://launchpad.net/~qtrvsimteam/+archive/ubuntu/ppa
For Arch, SUSE, Fedora and Debian https://software.opensuse.org/download.html?project=home%3Ajdupak&package=qtrvsim
Experimental Emscripten build can be accessed online https://dev.jakubdupak.com/qtrvsim/
QtRVSim version 0.9.0 release
- The first QtRVSim experimental release after switch to RISC-V
- The original QtMips project https://github.com/cvut/QtMips
- The memory model, visualization and packaging updated by Jakub Dupak
- The initial limited RV32 instruction set subset has been initiated by Max Hollmann
- The CPU diagram is slowly updated to match version prepared by Michal Stepanovsky
- Project coordination Pavel Pisa
- Students work was funded by RPAPS 2021 initiative at Czech Technical University in Prague Faculty of Electrical Engineering, https://fel.cvut.cz/
- We thanks for actual funding from followup project by Czech Technical University https://www.cvut.cz/
For Ubuntu use https://launchpad.net/~qtrvsimteam/+archive/ubuntu/ppa
For SUSE, Fedora and Debian https://software.opensuse.org/download.html?project=home%3Ajdupak&package=qtrvsim
Experimental Emscripten build can be accessed online https://dev.jakubdupak.com/qtrvsim/