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implement some FP32 instructions (fadd.s, fsub.s, flw, fsw) #134

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This pr is the follow up of #109.

Sry that because I didn't pass the test cases, I reviewed the code again and accidentally lost the last pr. Thanks to the help of @trdthg , he helped me to modify the test cases (because origin misa register stores supported extensions, so RVF is also needed to be add to misa?)

Now the code can pass the CI for now, and successfully execute those FP instructions.

@Jingqing3948 Jingqing3948 force-pushed the jingqing-temp-branch branch 3 times, most recently from cd9fc02 to 421d5c5 Compare May 13, 2024 09:57
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