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Warn on <literal>.asUInt|.asSInt(_: Int) #4764

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merged 1 commit into from
Mar 4, 2025

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jackkoenig
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Fixes #4733

Unfortunately, this is really hard to write a unit test for, but I did manually check it works (and it's using the same approach as we have been using for .U and .S). I'm also not sure that this is the best fix for 4733, but it works.

FYI @tymcauley

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The user probably forgot .W. Apply the same technique as used for .U|.S.

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The user probably forgot .W. Apply the same technique as used for .U|.S.
@jackkoenig jackkoenig added the Deprecation Deprecates an API, will be included in release notes label Mar 3, 2025
@jackkoenig jackkoenig added this to the 6.x milestone Mar 3, 2025
@jackkoenig jackkoenig requested a review from seldridge March 3, 2025 23:39
@mwachs5
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mwachs5 commented Mar 3, 2025

what is the actual change in behavior here? Without a test it's hard to tell

@jackkoenig
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jackkoenig commented Mar 4, 2025

what is the actual change in behavior here? Without a test it's hard to tell

val x: Int = 3
x.asUInt(8) // this is now a compile error
4.asUInt(10) // this is now a compile error

Full example:

class Foo(a: Int) extends Module {
  val w, x, y, z = IO(Output(UInt(8.W)))
  w := a.asUInt(8)
  x := 4.asUInt(8)
  y := 5.asUInt(8.W) // this is fine
  z := VecInit(1.U, 2.U, 3.U).asUInt // this is fine
}

This warns with (but I have warnings as errors so its an error):

[error] /Users/koenig/work/chisel-asuint-lint/src/main/scala/chisel-example.scala:13:16: Passing an Int to .asUInt is usually a mistake: It does *not* set the width; it does a bit extraction.
[error] Did you mean .asUInt(8.W)?
[error] If you do want bit extraction, use .asUInt.extract(8) instead.
[error]   w := a.asUInt(8)
[error]                ^
[error] /Users/koenig/work/chisel-asuint-lint/src/main/scala/chisel-example.scala:14:16: Passing an Int to .asUInt is usually a mistake: It does *not* set the width; it does a bit extraction.
[error] Did you mean .asUInt(8.W)?
[error] If you do want bit extraction, use .asUInt.extract(8) instead.
[error]   x := 4.asUInt(8)
[error]                ^
[error] two errors found

@mwachs5
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mwachs5 commented Mar 4, 2025

what about

zz := VecInit(1.U, 2.U, 3.U).asUInt(8)

what's the argument for keeping this fine?

@jackkoenig
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what about

zz := VecInit(1.U, 2.U, 3.U).asUInt(8)

what's the argument for keeping this fine?

Typically, the number you put is a width greater than the automatic width of the argument and you'll get an out-of-bounds index error. So basically, it's not usually fine.

That doesn't apply to literals for various reasons, arguably if you don't give them a width, they shouldn't really have a width so it's weird to enforce the minimum possible width on a subsequent bit extract. And subsequent bit extracts do sometimes happen, usually in loops or more complex control flow.

The main issue though, is that it's really hard to ban a chained apply after anything. @sequencer has suggested getting rid of apply for bit extraction, we could require everyone to explicitly write .extract(bit) or .extract(hi, lo). It certainly would avoid ambiguity issues this.

But rather than trying to tackle something so big, I figured I'd apply the fix we already have for .U and .S to .asUInt and .asSInt.

@tymcauley
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Looks great to me!

To be clear, this is emitted as a Scala warning, not a Chisel warning (as in this), correct? Presumably because we don't have access to the Builder in this macro?

@jackkoenig
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To be clear, this is emitted as a Scala warning, not a Chisel warning (as in this), correct? Presumably because we don't have access to the Builder in this macro?

Correct, Scala warnings are also configurable, just with an argument to scalac instead of to Chisel.

We could make this a Chisel time warning/error but IMO Scala-time is always best when possible and practical.

@jackkoenig jackkoenig merged commit 811bb46 into main Mar 4, 2025
18 checks passed
@jackkoenig jackkoenig deleted the warn-asuint-assint-extract branch March 4, 2025 16:13
@mergify mergify bot added the Backported This PR has been backported label Mar 4, 2025
chiselbot pushed a commit that referenced this pull request Mar 4, 2025
The user probably forgot .W. Apply the same technique as used for .U|.S.

(cherry picked from commit 811bb46)
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mergify bot commented Mar 4, 2025

backport

✅ Backports have been created

chiselbot added a commit that referenced this pull request Mar 4, 2025
The user probably forgot .W. Apply the same technique as used for .U|.S.

(cherry picked from commit 811bb46)

Co-authored-by: Jack Koenig <koenig@sifive.com>
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literal.asUInt(width) always returns a Bool
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