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404 Open 1,265 Closed
404 Open 1,265 Closed
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Issues list

system verilog "import" command not recognized (ERROR: syntax error, unexpected TOK_ID) pending-verification This issue is pending verification and/or reproduction
#4447 opened Jun 11, 2024 by titan73
2
Performance Issue: Synthesis Takes Too Long to Complete pending-verification This issue is pending verification and/or reproduction
#4445 opened Jun 11, 2024 by LoSyTe
3
Stub RTL Generation Feature feature-request
#4442 opened Jun 10, 2024 by Peter-Herrmann
Throws a segmentation fault if the 'input.blif' file's size is huge. pending-verification This issue is pending verification and/or reproduction
#4441 opened Jun 10, 2024 by dmanjun5
1
Clean up uses of #if(n)def EMSCRIPTEN
#4438 opened Jun 10, 2024 by nakengelhardt
Ensuring smooth Yosys-to-Synlig compatability and tracking feature-request
#4436 opened Jun 9, 2024 by chili-chips-ba
12
cell reference names appear to be truncated pending-verification This issue is pending verification and/or reproduction
#4435 opened Jun 7, 2024 by Cronus-38
Yosys Verilog Parsing Error: Unable to Synthesize After Reading File bug
#4427 opened Jun 4, 2024 by LoSyTe
1
2
formal: assert triggered a clock step too late pending-verification This issue is pending verification and/or reproduction
#4426 opened Jun 3, 2024 by NikLeberg
5
CXXRTL: >20x compile time regression with clang++-18 bug cxxrtl pending-verification This issue is pending verification and/or reproduction
#4419 opened May 27, 2024 by Wren6991
3
A topological loop is generated after using async2sync pending-verification This issue is pending verification and/or reproduction
#4414 opened May 24, 2024 by ZhiyuanYan
2
Yosys right shift error pending-verification This issue is pending verification and/or reproduction
#4413 opened May 24, 2024 by WeneneW
3
create a pip install package wheel for Windows feature-request
#4410 opened May 22, 2024 by eabase
3
Abnormal output pending-verification This issue is pending verification and/or reproduction
#4407 opened May 22, 2024 by WeneneW
make error 'abc' is not configured as a git submodule. pending-verification This issue is pending verification and/or reproduction
#4403 opened May 20, 2024 by Krishnakumarmohanraj
11
read_verilog doesn't respect signed keyword bug
#4402 opened May 18, 2024 by WeneneW
2
Yosys seems to handle bit operations on empty strings inconsistently with the original design. bug
#4395 opened May 13, 2024 by WeneneW
4
Wired-or (wor) wires generate $or / $reduce_or cells in output bug
#4389 opened May 10, 2024 by jswrightoc
3
No bad property in btor2 file generated from verilog (write_btor should error for $check cells) error handling Error handling and reporting
#4381 opened May 8, 2024 by gipsyh
3
Add support for SystemVerilog's ==? and !=? operators feature-request
#4374 opened May 4, 2024 by jmi2k
Inout can't be read with constant value feature-request
#4370 opened May 3, 2024 by alchitry
3
Spurious warnings "select out of bounds on signal" when there is no such thing ... bug
#4363 opened Apr 29, 2024 by smunaut
1
write_smt2: "-wires" option leads to inequivalent descriptions pending-verification This issue is pending verification and/or reproduction
#4361 opened Apr 27, 2024 by YikeZhou
opt: no "-purge" option but public names removed bug
#4357 opened Apr 25, 2024 by YikeZhou
2
Should -nomx8 be the default for the GateMate? pending-verification This issue is pending verification and/or reproduction
#4355 opened Apr 23, 2024 by spth
ProTip! Updated in the last three days: updated:>2024-06-08.