This is a fully functional, virtual RISC-V core, implemented in zig. (To be precise, it's an RV32I) You can find the relevant spec here.

Usage

The core expects unit tests at riscv-tests/isa. Download the git submodule and follow its instructions to compile the RISC-V unit tests. You need to have the RISC-V GNU Toolchain installed. In theory, it can run any RISC-V Elf.

Additional Ressources

• RISC-V assembly programmer guide
• Base instruction list