risc-v
Unlike most other ISA designs, the RISC-V ISA is provided under open source licenses that do not require fees to use. A number of companies are offering or have announced RISC-V hardware, open source operating systems with RISC-V support are available and the instruction set is supported in several popular software toolchains.
Notable features of the RISC-V ISA include a load–store architecture, bit patterns to simplify the multiplexers in a CPU, IEEE 754 floating-point, a design that is architecturally neutral, and placing most-significant bits at a fixed location to speed sign extension. The instruction set is designed for a wide range of uses. The base instruction set has a fixed length of 32-bit naturally aligned instructions, and the ISA supports variable length extensions where each instruction could be an any number of 16-bit parcels in length. Subsets support small embedded systems, personal computers, supercomputers with vector processors, and warehouse-scale 19 inch rack-mounted parallel computers.
Here are 1,689 public repositories matching this topic...
Open-source high-performance RISC-V processor
-
Updated
Jun 13, 2024 - Scala
A self-hosting and educational C optimizing compiler
-
Updated
Jun 13, 2024 - C
RT-Thread is an open source IoT real-time operating system (RTOS).
-
Updated
Jun 13, 2024 - C
The official repository for the gem5 computer-system architecture simulator.
-
Updated
Jun 13, 2024 - C++
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
-
Updated
Jun 12, 2024 - Scala
Lightweight justice for your single-board computer!
-
Updated
Jun 12, 2024 - Shell
Processing Unit with RISCV-32 / RISCV-64 / RISCV-128
-
Updated
Jun 12, 2024 - SystemVerilog