Simple Computer Architecture using direct mapped cache memory. Designed in VHDL and Quartus.
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Jun 30, 2020 - VHDL
Simple Computer Architecture using direct mapped cache memory. Designed in VHDL and Quartus.
Tournament Branch Predictor (Hybrid Predictor)
Implemented 5 stage pipe line. Fetch, Decode, Centralized Issue Queue. Branch prediction and forwarding.
Decimal-two's complement number converter. Project for "Computer Architecture"
🏗 💾 | Computer Architecture Course CEIT@AUT
📚 Computer science curriculum website
This is a project repository for Maham and Shiza Computer Architecture
Grad school, Adv Computer Architecture, Instruction Pipeline project. Pipelining is a technique where multiple instructions are overlapped during execution. Pipeline is divided into stages and these stages are connected with one another to form a pipe like structure. Instructions enter from one end and exit from another end. Pipelining increases…
7 Stage APEX Pipeline based on instructions flow in a Computer Architecture
Upgrading ARM9TDMI 32-bit processor original version.
Code from labs for COIS 2300 Computer Organization
This project implements a MIPS processor simulator in C++. It interprets a limited set of MIPS assembly, enabling the implementation of a functional processor. The system features an automated assembly-machine code translator and offers modes for testing and execution. Specialized modules handle operations like arithmetic, multiplexing, etc.
All codes Done during my Practical Session with Some Amazing Concepts
Simulates Tomasulo Algorithms with Reorder Buffer
Pipelined Processor for RISC-V Instruction Set
Website for the long-term mentoring program in computer architecture.
Some samples of my CS work from the 2019-2020 school year
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