{"payload":{"pageCount":1,"repositories":[{"type":"Public","name":"pythondata-cpu-cva6","owner":"litex-hub","isFork":false,"description":"Python module containing system_verilog files for cva6 cpu (for use with LiteX).","allTopics":[],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":1,"issueCount":0,"starsCount":2,"forksCount":4,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-06-05T20:13:47.369Z"}},{"type":"Public","name":"pythondata-cpu-ibex","owner":"litex-hub","isFork":false,"description":"Python module containing system_verilog files for ibex cpu (for use with LiteX).","allTopics":[],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":1,"issueCount":0,"starsCount":2,"forksCount":3,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-06-05T20:13:49.588Z"}},{"type":"Public","name":"pythondata-cpu-cva5","owner":"litex-hub","isFork":false,"description":"Python module containing system_verilog files for cva5 cpu (for use with LiteX).","allTopics":[],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":0,"issueCount":0,"starsCount":1,"forksCount":0,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-06-05T20:13:44.442Z"}},{"type":"Public","name":"pythondata-cpu-cv32e41p","owner":"litex-hub","isFork":false,"description":"Python module containing system_verilog files for cv32e41p cpu (for use with LiteX).","allTopics":[],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":0,"issueCount":0,"starsCount":1,"forksCount":1,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-06-05T20:13:42.520Z"}},{"type":"Public","name":"pythondata-cpu-cv32e40p","owner":"litex-hub","isFork":false,"description":"Python module containing system_verilog files for cv32e40p cpu (for use with LiteX).","allTopics":[],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":0,"issueCount":0,"starsCount":1,"forksCount":6,"license":"Other","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-06-05T20:13:40.546Z"}},{"type":"Public","name":"pythondata-cpu-blackparrot","owner":"litex-hub","isFork":false,"description":"Python module containing system_verilog files for blackparrot cpu (for use with LiteX).","allTopics":[],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":0,"issueCount":0,"starsCount":5,"forksCount":3,"license":"BSD 3-Clause \"New\" or \"Revised\" License","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-06-05T20:13:37.597Z"}},{"type":"Public","name":"pythondata-misc-opentitan","owner":"litex-hub","isFork":false,"description":"Python module containing resources files for opentitan misc (for use with LiteX).","allTopics":[],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":1,"issueCount":0,"starsCount":2,"forksCount":1,"license":"Apache License 2.0","participation":[0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2022-11-09T03:09:26.122Z"}},{"type":"Public","name":"pythondata-cpu-cv32e40x","owner":"litex-hub","isFork":false,"description":"Python module containing system_verilog files for cv32e40x cpu (for use with LiteX).","allTopics":[],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":0,"issueCount":0,"starsCount":0,"forksCount":0,"license":"Apache License 2.0","participation":[0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2022-11-02T12:25:32.264Z"}},{"type":"Public","name":"pythondata-cpu-cv32e40s","owner":"litex-hub","isFork":false,"description":"Python module containing system_verilog files for cv32e40s cpu (for use with LiteX).","allTopics":[],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":0,"issueCount":0,"starsCount":1,"forksCount":0,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2022-11-02T09:16:13.953Z"}}],"repositoryCount":9,"userInfo":null,"searchable":true,"definitions":[],"typeFilters":[{"id":"all","text":"All"},{"id":"public","text":"Public"},{"id":"source","text":"Sources"},{"id":"fork","text":"Forks"},{"id":"archived","text":"Archived"},{"id":"template","text":"Templates"}],"compactMode":false},"title":"Repositories"}