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swankmania_HDL.flow.rpt
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swankmania_HDL.flow.rpt
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Flow report for swankmania_HDL
Mon Nov 26 17:50:47 2007
Quartus II Version 7.2 Build 151 09/26/2007 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Flow Summary
3. Flow Settings
4. Flow Non-Default Global Settings
5. Flow Elapsed Time
6. Flow Log
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+------------------------------------------------------------------------------+
; Flow Summary ;
+------------------------------------+-----------------------------------------+
; Flow Status ; Successful - Mon Nov 26 17:50:47 2007 ;
; Quartus II Version ; 7.2 Build 151 09/26/2007 SJ Web Edition ;
; Revision Name ; swankmania_HDL ;
; Top-level Entity Name ; swankmania_HDL ;
; Family ; Cyclone II ;
; Device ; EP2C35F672C6 ;
; Timing Models ; Final ;
; Met timing requirements ; Yes ;
; Total logic elements ; 1,042 / 33,216 ( 3 % ) ;
; Total combinational functions ; 990 / 33,216 ( 3 % ) ;
; Dedicated logic registers ; 296 / 33,216 ( < 1 % ) ;
; Total registers ; 296 ;
; Total pins ; 196 / 475 ( 41 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 355,840 / 483,840 ( 74 % ) ;
; Embedded Multiplier 9-bit elements ; 0 / 70 ( 0 % ) ;
; Total PLLs ; 1 / 4 ( 25 % ) ;
+------------------------------------+-----------------------------------------+
+-----------------------------------------+
; Flow Settings ;
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 11/26/2007 17:48:57 ;
; Main task ; Compilation ;
; Revision Name ; swankmania_HDL ;
+-------------------+---------------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings ;
+---------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------+-------------+------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+---------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------+-------------+------------+
; ADV_NETLIST_OPT_SYNTH_GATE_RETIME ; On ; Off ; -- ; -- ;
; ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ; On ; Off ; -- ; -- ;
; CYCLONEII_OPTIMIZATION_TECHNIQUE ; Speed ; Balanced ; -- ; -- ;
; ENABLE_CLOCK_LATENCY ; On ; Off ; -- ; -- ;
; ENABLE_DA_RULE ; C101, C102, C103, C104, C105, C106, R101, R102, R103, R104, R105, T101, T102, A101, A102, A103, A104, A105, A106, A107, A108, A109, A110, S101, S102, S103, S104, D101, D102, D103, H101, H102, M101, M102, M103, M104, M105 ; -- ; -- ; -- ;
; ENABLE_RECOVERY_REMOVAL_ANALYSIS ; On ; Off ; -- ; -- ;
; MUX_RESTRUCTURE ; Off ; Auto ; -- ; -- ;
; OPTIMIZE_FAST_CORNER_TIMING ; On ; Off ; -- ; -- ;
; OPTIMIZE_POWER_DURING_SYNTHESIS ; Off ; Normal compilation ; -- ; -- ;
; PARTITION_COLOR ; 2147039 ; -- ; -- ; Top ;
; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ;
; PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ; On ; Off ; -- ; -- ;
; PHYSICAL_SYNTHESIS_COMBO_LOGIC ; On ; Off ; -- ; -- ;
; PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ; On ; Off ; -- ; -- ;
; PHYSICAL_SYNTHESIS_EFFORT ; Extra ; Normal ; -- ; -- ;
; PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ; On ; Off ; -- ; -- ;
; PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ; On ; Off ; -- ; -- ;
; PHYSICAL_SYNTHESIS_REGISTER_RETIMING ; On ; Off ; -- ; -- ;
; POWER_BOARD_THERMAL_MODEL ; None (CONSERVATIVE) ; -- ; -- ; -- ;
; POWER_PRESET_COOLING_SOLUTION ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; -- ; -- ; -- ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; On ; Off ; -- ; -- ;
; ROUTER_TIMING_OPTIMIZATION_LEVEL ; MAXIMUM ; Normal ; -- ; -- ;
; SMART_RECOMPILE ; On ; Off ; -- ; -- ;
; STATE_MACHINE_PROCESSING ; One-Hot ; Auto ; -- ; -- ;
; USER_LIBRARIES ; lib ; -- ; -- ; -- ;
; VERILOG_INPUT_VERSION ; SystemVerilog_2005 ; Verilog_2001 ; -- ; -- ;
; VERILOG_SHOW_LMF_MAPPING_MESSAGES ; Off ; -- ; -- ; -- ;
+---------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------+-------------+------------+
+------------------------------------------------------------------+
; Flow Elapsed Time ;
+-------------------------+--------------+-------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ;
+-------------------------+--------------+-------------------------+
; Analysis & Synthesis ; 00:00:13 ; 1.0 ;
; Fitter ; 00:01:20 ; 1.0 ;
; Assembler ; 00:00:11 ; 1.0 ;
; Classic Timing Analyzer ; 00:00:02 ; 1.0 ;
; Total ; 00:01:46 ; -- ;
+-------------------------+--------------+-------------------------+
------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off swankmania_HDL -c swankmania_HDL
quartus_fit --read_settings_files=off --write_settings_files=off swankmania_HDL -c swankmania_HDL
quartus_asm --read_settings_files=off --write_settings_files=off swankmania_HDL -c swankmania_HDL
quartus_tan --read_settings_files=off --write_settings_files=off swankmania_HDL -c swankmania_HDL --timing_analysis_only