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Install Empty GCD Sync Protocol After SyncCacheConfig() #228

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TaylorBeebe
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Description

With the addition of the following commit in MU_BASECORE, the ordering of memory protection initialization and the GCD sync has been flipped so the GCD sync occurs first: microsoft/mu_basecore@144e3fe

This reverse ordering was done to support RP on free memory because if the initialization was done first then the allocate memory calls during GCD sync would cause page faults because the attributes cannot be changed during the syncing process.

This PR installs the GCD sync complete protocol so the memory protection initialization routine is signaled.

  • Impacts functionality?
    • Functionality - Does the change ultimately impact how firmware functions?
    • Examples: Add a new library, publish a new PPI, update an algorithm, ...
  • Impacts security?
    • Security - Does the change have a direct security impact on an application,
      flow, or firmware?
    • Examples: Crypto algorithm change, buffer overflow fix, parameter
      validation improvement, ...
  • Breaking change?
    • Breaking change - Will anyone consuming this change experience a break
      in build or boot behavior?
    • Examples: Add a new library class, move a module to a different repo, call
      a function in a new library class in a pre-existing module, ...
  • Includes tests?
    • Tests - Does the change include any explicit test code?
    • Examples: Unit tests, integration tests, robot tests, ...
  • Includes documentation?
    • Documentation - Does the change contain explicit documentation additions
      outside direct code modifications (and comments)?
    • Examples: Update readme file, add feature readme file, link to documentation
      on an a separate Web page, ...

How This Was Tested

Tested by booting SBSA to shell with RP on free memory active

Integration Instructions

N/A

Sorry, something went wrong.

@TaylorBeebe TaylorBeebe requested review from os-d and apop5 April 26, 2024 23:37
@github-actions github-actions bot added the impact:security Has a security impact label Apr 26, 2024
@TaylorBeebe TaylorBeebe changed the title Install Empty GCD Sync Protocol After SyncCacheConfig() to Match UefiCpuPkg CpuDxe Install Empty GCD Sync Protocol After SyncCacheConfig() Apr 27, 2024
@TaylorBeebe TaylorBeebe merged commit c20bc5b into microsoft:release/202311 Apr 27, 2024
14 checks passed
@TaylorBeebe TaylorBeebe deleted the install_gcd_sync_protocol branch April 27, 2024 15:59
os-d pushed a commit to os-d/mu_silicon_arm_tiano that referenced this pull request Jul 19, 2024
## Description

With the addition of the following commit in MU_BASECORE, the ordering
of memory protection initialization and the GCD sync has been flipped so
the GCD sync occurs first:
microsoft/mu_basecore@144e3fe

This reverse ordering was done to support RP on free memory because if
the initialization was done first then the allocate memory calls during
GCD sync would cause page faults because the attributes cannot be
changed during the syncing process.

This PR installs the GCD sync complete protocol so the memory protection
initialization routine is signaled.

- [x] Impacts functionality?
- **Functionality** - Does the change ultimately impact how firmware
functions?
- Examples: Add a new library, publish a new PPI, update an algorithm,
...
- [x] Impacts security?
- **Security** - Does the change have a direct security impact on an
application,
    flow, or firmware?
  - Examples: Crypto algorithm change, buffer overflow fix, parameter
    validation improvement, ...
- [ ] Breaking change?
- **Breaking change** - Will anyone consuming this change experience a
break
    in build or boot behavior?
- Examples: Add a new library class, move a module to a different repo,
call
    a function in a new library class in a pre-existing module, ...
- [ ] Includes tests?
  - **Tests** - Does the change include any explicit test code?
  - Examples: Unit tests, integration tests, robot tests, ...
- [ ] Includes documentation?
- **Documentation** - Does the change contain explicit documentation
additions
    outside direct code modifications (and comments)?
- Examples: Update readme file, add feature readme file, link to
documentation
    on an a separate Web page, ...

## How This Was Tested

Tested by booting SBSA to shell with RP on free memory active

## Integration Instructions

N/A
os-d pushed a commit to os-d/mu_silicon_arm_tiano that referenced this pull request Jul 19, 2024
## Description

With the addition of the following commit in MU_BASECORE, the ordering
of memory protection initialization and the GCD sync has been flipped so
the GCD sync occurs first:
microsoft/mu_basecore@144e3fe

This reverse ordering was done to support RP on free memory because if
the initialization was done first then the allocate memory calls during
GCD sync would cause page faults because the attributes cannot be
changed during the syncing process.

This PR installs the GCD sync complete protocol so the memory protection
initialization routine is signaled.

- [x] Impacts functionality?
- **Functionality** - Does the change ultimately impact how firmware
functions?
- Examples: Add a new library, publish a new PPI, update an algorithm,
...
- [x] Impacts security?
- **Security** - Does the change have a direct security impact on an
application,
    flow, or firmware?
  - Examples: Crypto algorithm change, buffer overflow fix, parameter
    validation improvement, ...
- [ ] Breaking change?
- **Breaking change** - Will anyone consuming this change experience a
break
    in build or boot behavior?
- Examples: Add a new library class, move a module to a different repo,
call
    a function in a new library class in a pre-existing module, ...
- [ ] Includes tests?
  - **Tests** - Does the change include any explicit test code?
  - Examples: Unit tests, integration tests, robot tests, ...
- [ ] Includes documentation?
- **Documentation** - Does the change contain explicit documentation
additions
    outside direct code modifications (and comments)?
- Examples: Update readme file, add feature readme file, link to
documentation
    on an a separate Web page, ...

## How This Was Tested

Tested by booting SBSA to shell with RP on free memory active

## Integration Instructions

N/A
os-d pushed a commit to os-d/mu_silicon_arm_tiano that referenced this pull request Jul 19, 2024
## Description

With the addition of the following commit in MU_BASECORE, the ordering
of memory protection initialization and the GCD sync has been flipped so
the GCD sync occurs first:
microsoft/mu_basecore@144e3fe

This reverse ordering was done to support RP on free memory because if
the initialization was done first then the allocate memory calls during
GCD sync would cause page faults because the attributes cannot be
changed during the syncing process.

This PR installs the GCD sync complete protocol so the memory protection
initialization routine is signaled.

- [x] Impacts functionality?
- **Functionality** - Does the change ultimately impact how firmware
functions?
- Examples: Add a new library, publish a new PPI, update an algorithm,
...
- [x] Impacts security?
- **Security** - Does the change have a direct security impact on an
application,
    flow, or firmware?
  - Examples: Crypto algorithm change, buffer overflow fix, parameter
    validation improvement, ...
- [ ] Breaking change?
- **Breaking change** - Will anyone consuming this change experience a
break
    in build or boot behavior?
- Examples: Add a new library class, move a module to a different repo,
call
    a function in a new library class in a pre-existing module, ...
- [ ] Includes tests?
  - **Tests** - Does the change include any explicit test code?
  - Examples: Unit tests, integration tests, robot tests, ...
- [ ] Includes documentation?
- **Documentation** - Does the change contain explicit documentation
additions
    outside direct code modifications (and comments)?
- Examples: Update readme file, add feature readme file, link to
documentation
    on an a separate Web page, ...

## How This Was Tested

Tested by booting SBSA to shell with RP on free memory active

## Integration Instructions

N/A
os-d pushed a commit to os-d/mu_silicon_arm_tiano that referenced this pull request Jul 19, 2024
## Description

With the addition of the following commit in MU_BASECORE, the ordering
of memory protection initialization and the GCD sync has been flipped so
the GCD sync occurs first:
microsoft/mu_basecore@144e3fe

This reverse ordering was done to support RP on free memory because if
the initialization was done first then the allocate memory calls during
GCD sync would cause page faults because the attributes cannot be
changed during the syncing process.

This PR installs the GCD sync complete protocol so the memory protection
initialization routine is signaled.

- [x] Impacts functionality?
- **Functionality** - Does the change ultimately impact how firmware
functions?
- Examples: Add a new library, publish a new PPI, update an algorithm,
...
- [x] Impacts security?
- **Security** - Does the change have a direct security impact on an
application,
    flow, or firmware?
  - Examples: Crypto algorithm change, buffer overflow fix, parameter
    validation improvement, ...
- [ ] Breaking change?
- **Breaking change** - Will anyone consuming this change experience a
break
    in build or boot behavior?
- Examples: Add a new library class, move a module to a different repo,
call
    a function in a new library class in a pre-existing module, ...
- [ ] Includes tests?
  - **Tests** - Does the change include any explicit test code?
  - Examples: Unit tests, integration tests, robot tests, ...
- [ ] Includes documentation?
- **Documentation** - Does the change contain explicit documentation
additions
    outside direct code modifications (and comments)?
- Examples: Update readme file, add feature readme file, link to
documentation
    on an a separate Web page, ...

## How This Was Tested

Tested by booting SBSA to shell with RP on free memory active

## Integration Instructions

N/A
os-d pushed a commit to os-d/mu_silicon_arm_tiano that referenced this pull request Jul 22, 2024
## Description

With the addition of the following commit in MU_BASECORE, the ordering
of memory protection initialization and the GCD sync has been flipped so
the GCD sync occurs first:
microsoft/mu_basecore@144e3fe

This reverse ordering was done to support RP on free memory because if
the initialization was done first then the allocate memory calls during
GCD sync would cause page faults because the attributes cannot be
changed during the syncing process.

This PR installs the GCD sync complete protocol so the memory protection
initialization routine is signaled.

- [x] Impacts functionality?
- **Functionality** - Does the change ultimately impact how firmware
functions?
- Examples: Add a new library, publish a new PPI, update an algorithm,
...
- [x] Impacts security?
- **Security** - Does the change have a direct security impact on an
application,
    flow, or firmware?
  - Examples: Crypto algorithm change, buffer overflow fix, parameter
    validation improvement, ...
- [ ] Breaking change?
- **Breaking change** - Will anyone consuming this change experience a
break
    in build or boot behavior?
- Examples: Add a new library class, move a module to a different repo,
call
    a function in a new library class in a pre-existing module, ...
- [ ] Includes tests?
  - **Tests** - Does the change include any explicit test code?
  - Examples: Unit tests, integration tests, robot tests, ...
- [ ] Includes documentation?
- **Documentation** - Does the change contain explicit documentation
additions
    outside direct code modifications (and comments)?
- Examples: Update readme file, add feature readme file, link to
documentation
    on an a separate Web page, ...

## How This Was Tested

Tested by booting SBSA to shell with RP on free memory active

## Integration Instructions

N/A
os-d pushed a commit that referenced this pull request Jul 22, 2024
## Description

With the addition of the following commit in MU_BASECORE, the ordering
of memory protection initialization and the GCD sync has been flipped so
the GCD sync occurs first:
microsoft/mu_basecore@144e3fe

This reverse ordering was done to support RP on free memory because if
the initialization was done first then the allocate memory calls during
GCD sync would cause page faults because the attributes cannot be
changed during the syncing process.

This PR installs the GCD sync complete protocol so the memory protection
initialization routine is signaled.

- [x] Impacts functionality?
- **Functionality** - Does the change ultimately impact how firmware
functions?
- Examples: Add a new library, publish a new PPI, update an algorithm,
...
- [x] Impacts security?
- **Security** - Does the change have a direct security impact on an
application,
    flow, or firmware?
  - Examples: Crypto algorithm change, buffer overflow fix, parameter
    validation improvement, ...
- [ ] Breaking change?
- **Breaking change** - Will anyone consuming this change experience a
break
    in build or boot behavior?
- Examples: Add a new library class, move a module to a different repo,
call
    a function in a new library class in a pre-existing module, ...
- [ ] Includes tests?
  - **Tests** - Does the change include any explicit test code?
  - Examples: Unit tests, integration tests, robot tests, ...
- [ ] Includes documentation?
- **Documentation** - Does the change contain explicit documentation
additions
    outside direct code modifications (and comments)?
- Examples: Update readme file, add feature readme file, link to
documentation
    on an a separate Web page, ...

## How This Was Tested

Tested by booting SBSA to shell with RP on free memory active

## Integration Instructions

N/A
apop5 pushed a commit to apop5/mu_silicon_arm_tiano that referenced this pull request Jan 17, 2025
## Description

With the addition of the following commit in MU_BASECORE, the ordering
of memory protection initialization and the GCD sync has been flipped so
the GCD sync occurs first:
microsoft/mu_basecore@144e3fe

This reverse ordering was done to support RP on free memory because if
the initialization was done first then the allocate memory calls during
GCD sync would cause page faults because the attributes cannot be
changed during the syncing process.

This PR installs the GCD sync complete protocol so the memory protection
initialization routine is signaled.

- [x] Impacts functionality?
- **Functionality** - Does the change ultimately impact how firmware
functions?
- Examples: Add a new library, publish a new PPI, update an algorithm,
...
- [x] Impacts security?
- **Security** - Does the change have a direct security impact on an
application,
    flow, or firmware?
  - Examples: Crypto algorithm change, buffer overflow fix, parameter
    validation improvement, ...
- [ ] Breaking change?
- **Breaking change** - Will anyone consuming this change experience a
break
    in build or boot behavior?
- Examples: Add a new library class, move a module to a different repo,
call
    a function in a new library class in a pre-existing module, ...
- [ ] Includes tests?
  - **Tests** - Does the change include any explicit test code?
  - Examples: Unit tests, integration tests, robot tests, ...
- [ ] Includes documentation?
- **Documentation** - Does the change contain explicit documentation
additions
    outside direct code modifications (and comments)?
- Examples: Update readme file, add feature readme file, link to
documentation
    on an a separate Web page, ...

## How This Was Tested

Tested by booting SBSA to shell with RP on free memory active

## Integration Instructions

N/A
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3 participants