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(riscv_expand_epilogue): Handle offset\n\tbeing sum of two S12.\n\nTested-by: Patrick O'Neill <patrick@rivosinc.com> # pre-commit-CI #1569\nSigned-off-by: Vineet Gupta <vineetg@rivosinc.com>","shortMessageHtmlLink":"RISC-V: avoid LUI based const mat in alloca epilogue expansion"}},{"before":"786597185d544b65723a419825c488bcae1cffcc","after":"b2bb49d6a77e4568c0b91db17b2599f5929fb85b","ref":"refs/heads/releases/gcc-14","pushedAt":"2024-05-21T19:13:29.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"kraj","name":"Khem Raj","path":"/kraj","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/465279?s=80&v=4"},"commit":{"message":"match: Disable `(type)zero_one_valuep*CST` for 1bit signed types [PR115154]\n\nThe problem here is the pattern added in r13-1162-g9991d84d2a8435\nassumes that it is well defined to multiply zero_one_valuep by the truncated\nconverted integer constant. It is well defined for all types except for signed 1bit types.\nWhere `a * -1` is produced which is undefined/\nSo disable this pattern for 1bit signed types.\n\nNote the pattern added in r14-3432-gddd64a6ec3b38e is able to workaround the undefinedness except when\n`-fsanitize=undefined` is turned on, this is why I added a testcase for that.\n\nBootstrapped and tested on x86_64-linux-gnu with no regressions.\n\n\tPR tree-optimization/115154\n\ngcc/ChangeLog:\n\n\t* match.pd (convert (mult zero_one_valued_p@1 INTEGER_CST@2)): Disable\n\tfor 1bit signed types.\n\ngcc/testsuite/ChangeLog:\n\n\t* c-c++-common/ubsan/signed1bitfield-1.c: New test.\n\t* gcc.c-torture/execute/signed1bitfield-1.c: New test.\n\nSigned-off-by: Andrew Pinski <quic_apinski@quicinc.com>\n(cherry picked from commit 49c87d22535ac4f8aacf088b3f462861c26cacb4)","shortMessageHtmlLink":"match: Disable <code>(type)zero_one_valuep*CST</code> for 1bit signed types [PR1…"}},{"before":"a021b585532ada45b6ab4dc9d8df2707d3585ef3","after":"c827f46d8652d7a089e614302a4cffb6b192284d","ref":"refs/heads/releases/gcc-13","pushedAt":"2024-05-21T19:13:28.000Z","pushType":"push","commitsCount":5,"pusher":{"login":"kraj","name":"Khem Raj","path":"/kraj","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/465279?s=80&v=4"},"commit":{"message":"testsuite: Adjust pr113359-2_*.c with unsigned long long [PR114662]\n\npr113359-2_*.c define a struct having unsigned long type\nmembers ay and az which have 4 bytes size at -m32, while\nthe related constants CL1 and CL2 used for equality check\nare always 8 bytes, it makes compiler consider the below\n\n  69   if (a.ay != CL1)\n  70     __builtin_abort ();\n\nalways to abort and optimize away the following call to\ngetb, which leads to the expected wpa dumping on\n\"Semantic equality\" missing.\n\nThis patch is to modify the types with unsigned long long\naccordingly.\n\n\tPR testsuite/114662\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.dg/lto/pr113359-2_0.c: Use unsigned long long instead of\n\tunsigned long.\n\t* gcc.dg/lto/pr113359-2_1.c: Likewise.\n\n(cherry picked from commit 4923ed49b93352bcf9e43cafac38345e4a54c3f8)","shortMessageHtmlLink":"testsuite: Adjust pr113359-2_*.c with unsigned long long [PR114662]"}},{"before":"0ebaffccb294d90184ad78367de66b6307de3ac0","after":"9926c40a902edbc665919d508ef0c36f362f9c41","ref":"refs/heads/master","pushedAt":"2024-05-21T19:13:20.000Z","pushType":"push","commitsCount":41,"pusher":{"login":"kraj","name":"Khem Raj","path":"/kraj","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/465279?s=80&v=4"},"commit":{"message":"RISC-V: avoid LUI based const mat in alloca epilogue expansion\n\nThis is continuing on the prev patch in function epilogue expansion.\nBroken out of easy of review.\n\ngcc/ChangeLog:\n\t* config/riscv/riscv.cc (riscv_expand_epilogue): Handle offset\n\tbeing sum of two S12.\n\nTested-by: Patrick O'Neill <patrick@rivosinc.com> # pre-commit-CI #1569\nSigned-off-by: Vineet Gupta <vineetg@rivosinc.com>","shortMessageHtmlLink":"RISC-V: avoid LUI based const mat in alloca epilogue expansion"}},{"before":"e14c673ea9ab2eca5de4db91b478f0b5297ef321","after":"0ebaffccb294d90184ad78367de66b6307de3ac0","ref":"refs/heads/trunk","pushedAt":"2024-05-21T07:23:18.000Z","pushType":"push","commitsCount":21,"pusher":{"login":"kraj","name":"Khem Raj","path":"/kraj","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/465279?s=80&v=4"},"commit":{"message":"Use pblendw instead of pand to clear upper 16 bits.\n\nFor vec_pack_truncv8si/v4si w/o AVX512,\n(const_vector:v4si (const_int 0xffff) x4) is used as mask to clear\nupper 16 bits, but vpblendw with zero_vector can also be used, and\nzero vector is cheaper than (const_vector:v4si (const_int 0xffff) x4).\n\ngcc/ChangeLog:\n\tPR target/114427\n\t* config/i386/i386-expand.cc (expand_vec_perm_even_odd_pack):\n\tUse pblendw instead of pand to clear upper bits.\n\ngcc/testsuite/ChangeLog:\n\t* gcc.target/i386/pr114427.c: New test.","shortMessageHtmlLink":"Use pblendw instead of pand to clear upper 16 bits."}},{"before":"a9837934203d41c96b5cf05e34f68c0d3311c973","after":"786597185d544b65723a419825c488bcae1cffcc","ref":"refs/heads/releases/gcc-14","pushedAt":"2024-05-21T07:22:46.000Z","pushType":"push","commitsCount":2,"pusher":{"login":"kraj","name":"Khem Raj","path":"/kraj","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/465279?s=80&v=4"},"commit":{"message":"Daily bump.","shortMessageHtmlLink":"Daily bump."}},{"before":"441602347fa29ae6fa8055853c5f262e35c92c8b","after":"a021b585532ada45b6ab4dc9d8df2707d3585ef3","ref":"refs/heads/releases/gcc-13","pushedAt":"2024-05-21T07:22:44.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"kraj","name":"Khem Raj","path":"/kraj","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/465279?s=80&v=4"},"commit":{"message":"Daily bump.","shortMessageHtmlLink":"Daily bump."}},{"before":"2f0c2cc25cd8d20d3dc172ff47ed4c3b50fc20db","after":"113ddbe0726e4abbd0f4789eee0d0fbee80bee81","ref":"refs/heads/releases/gcc-12","pushedAt":"2024-05-21T07:22:43.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"kraj","name":"Khem Raj","path":"/kraj","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/465279?s=80&v=4"},"commit":{"message":"Daily bump.","shortMessageHtmlLink":"Daily bump."}},{"before":"0ee06466f7667db12d866679cae251697076a06a","after":"75113e2e774fe7d0252da693cd3a1def2b982a13","ref":"refs/heads/releases/gcc-11","pushedAt":"2024-05-21T07:22:41.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"kraj","name":"Khem Raj","path":"/kraj","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/465279?s=80&v=4"},"commit":{"message":"Daily bump.","shortMessageHtmlLink":"Daily bump."}},{"before":"e14c673ea9ab2eca5de4db91b478f0b5297ef321","after":"0ebaffccb294d90184ad78367de66b6307de3ac0","ref":"refs/heads/master","pushedAt":"2024-05-21T07:22:35.000Z","pushType":"push","commitsCount":21,"pusher":{"login":"kraj","name":"Khem Raj","path":"/kraj","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/465279?s=80&v=4"},"commit":{"message":"Use pblendw instead of pand to clear upper 16 bits.\n\nFor vec_pack_truncv8si/v4si w/o AVX512,\n(const_vector:v4si (const_int 0xffff) x4) is used as mask to clear\nupper 16 bits, but vpblendw with zero_vector can also be used, and\nzero vector is cheaper than (const_vector:v4si (const_int 0xffff) x4).\n\ngcc/ChangeLog:\n\tPR target/114427\n\t* config/i386/i386-expand.cc (expand_vec_perm_even_odd_pack):\n\tUse pblendw instead of pand to clear upper bits.\n\ngcc/testsuite/ChangeLog:\n\t* gcc.target/i386/pr114427.c: New test.","shortMessageHtmlLink":"Use pblendw instead of pand to clear upper 16 bits."}},{"before":"755eacca6df4360f73784bd3cba389f09ad51a2c","after":"6bcb1f3c2614df70d66da29983ef55d9267a3652","ref":"refs/heads/oe/master","pushedAt":"2024-05-21T05:04:19.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"kraj","name":"Khem Raj","path":"/kraj","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/465279?s=80&v=4"},"commit":{"message":"gcc testsuite tweaks for mips/OE\n\nDisable loongson-mmi runtine, qemu doesn't appear to fully support them even if some\nof the instruction decoding is there.\n\nAlso disable MSA mips runtime extensions. For some reason qemu appears to accept the test\ncode when it shouldn't. Our selected MIPS cpu for QEMU doesn't support them.\n\nMIPS is unusual in the gcc testsuite as it uses EFFECTIVE_TARGETS and loops\nmultiple times through the vector testsuite. In the case of the two above, we can\ncompile/link them but not run them. Even with the runtime disabled, if the code\nmarks it as a runtime test, it will elevate itself to that. Setting the default\ntarget to compile therefore isn't enough.\n\nTherefore add code to downgrade runtime tests to link tests if the hardware\nsupport isn't there to run them. This avoids thousands of test failures. To do\nthis we have to hook downgrade code into the main test runner.\n\nEnable that downgrading for other cases where hardware to run vector extensions is\nunavailable to remove test failures on other architectures too.\n\nAlso, for gcc.target tests, add checks on wheter loongson or msa code can\nbe run before trying that, allowing downgrading of tests there to work too.\n\nUpstream-Status: Pending\n\n[Parts of the patch may be able to be split off and acceptable to upstream with\ndiscussion. Need to investigate why qemu-user passes the 'bad' instructions']\n\nSigned-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>\nSigned-off-by: Khem Raj <raj.khem@gmail.com>","shortMessageHtmlLink":"gcc testsuite tweaks for mips/OE"}}],"hasNextPage":true,"hasPreviousPage":false,"activityType":"all","actor":null,"timePeriod":"all","sort":"DESC","perPage":30,"cursor":"djE6ks8AAAAEUbN9MQA","startCursor":null,"endCursor":null}},"title":"Activity · kraj/gcc"}