fix up extra waveform dump behavior in svsim

[Emin017]

When added require statement in ChiselSim/svsim, the delay value will be set to 0, which will cause an extra dump waveform behavior. So we only call eval_step once to update the design model.

This will fix #4516.

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• Did you add Scaladoc to every public function/method?
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Type of Improvement

• Bugfix

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[jackkoenig]

Thanks!