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base repository: chipsalliance/chisel
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base: v6.6.0
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head repository: chipsalliance/chisel
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compare: v6.7.0
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  • 17 commits
  • 72 files changed
  • 9 contributors

Commits on Nov 26, 2024

  1. Update CD permissions for uploading release artifacts (#4529) (#4531)

    Also bump softprops/action-gh-release to v2.1.0.
    
    (cherry picked from commit 25d00af)
    
    Co-authored-by: Jack Koenig <koenig@sifive.com>
    mergify[bot] and jackkoenig authored Nov 26, 2024
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    038e38c View commit details

Commits on Jan 7, 2025

  1. fix typo in SourceInfoTransform.scala (#4594) (#4597)

    (cherry picked from commit 4177bfa)
    
    Co-authored-by: qiming chu <cchuqiming@gmail.com>
    mergify[bot] and Emin017 authored Jan 7, 2025
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    205b95f View commit details
  2. fix up extra waveform dump behavior in svsim (#4592) (#4600)

    When added require statement in ChiselSim/svsim, the delay value will be
    set to 0, which will cause an extra dump waveform behavior. So we only
    call `eval_step` once to update the design model
    
    (cherry picked from commit 3380196)
    
    Co-authored-by: qiming chu <cchuqiming@gmail.com>
    mergify[bot] and Emin017 authored Jan 7, 2025
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    158d66b View commit details

Commits on Jan 9, 2025

  1. Fixes sendBits()'s handling of signed numbers in svsim (#4599) (#…

    …4606)
    
    (cherry picked from commit d4d3e97)
    
    Co-authored-by: Jason Wang <174672328+AptInit@users.noreply.github.com>
    jackkoenig and AptInit authored Jan 9, 2025
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    d9c2f28 View commit details

Commits on Jan 10, 2025

  1. Enable MiMa for v6.6.0 (#4527)

    chiselbot authored Jan 10, 2025
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    8f76395 View commit details

Commits on Feb 4, 2025

  1. Speedup Computation for whether Aggregates containsProbe (#4656) (#4664)

    * save the elementContainsProbes for an Aggregate to speed up various computations
    * add unit tests for ContainsProbe
    
    (cherry picked from commit c9cecfa)
    
    Co-authored-by: Megan Wachs <megan@sifive.com>
    chiselbot and mwachs5 authored Feb 4, 2025
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    6b7429a View commit details

Commits on Feb 14, 2025

  1. Enforce deterministic FibonacciLFSR reductions (#4688) (#4690)

    (cherry picked from commit 63b129d)
    
    Co-authored-by: Jerry Zhao <jerryz123@berkeley.edu>
    chiselbot and jerryz123 authored Feb 14, 2025
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    43d9868 View commit details
  2. Cross-compile the plugin for Scala 2.13.16 (#4692)

    jackkoenig authored Feb 14, 2025
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    bbefcbe View commit details
  3. Add ElaboratedCircuit and deprecate use of internal ir Circuit (backp…

    …ort #4683) (#4693)
    
    * Add ElaboratedCircuit and deprecate use of internal ir Circuit (#4683)
    
    Change ChiselCircuitAnnotation and CircuitSerializationAnnotation to no
    longer be case classes to help with the transition to ElaboratedCircuit.
    
    (cherry picked from commit 4d75573)
    
    # Conflicts:
    #	core/src/main/scala/chisel3/experimental/hierarchy/core/Definition.scala
    #	core/src/main/scala/chisel3/internal/Builder.scala
    #	src/main/scala/chisel3/stage/ChiselOptions.scala
    #	src/main/scala/chisel3/stage/phases/AddImplicitOutputAnnotationFile.scala
    #	src/main/scala/chisel3/stage/phases/AddImplicitOutputFile.scala
    #	src/main/scala/chisel3/stage/phases/Convert.scala
    #	src/main/scala/chisel3/stage/phases/Elaborate.scala
    #	src/test/scala/circtTests/stage/ChiselStageSpec.scala
    
    * Resolve backport conflicts
    
    * MiMa waive package private constructor change
    
    * Fix ScalaDoc
    
    ---------
    
    Co-authored-by: Jack Koenig <koenig@sifive.com>
    Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
    3 people authored Feb 14, 2025
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    118079b View commit details

Commits on Feb 15, 2025

  1. Add safer Chisel annotation API, deprecate old ones (backport #4643) (#…

    …4697)
    
    * Add safer Chisel annotation API, deprecate old ones (#4643)
    
    The new one enables safety checks and smarter logic for views.
    
    (cherry picked from commit a95cfe4)
    
    # Conflicts:
    #	build.mill
    #	build.sbt
    #	core/src/main/scala/chisel3/Annotation.scala
    #	core/src/main/scala/chisel3/ChiselEnum.scala
    #	core/src/main/scala/chisel3/Module.scala
    #	core/src/main/scala/chisel3/dontTouch.scala
    #	core/src/main/scala/chisel3/experimental/hierarchy/core/Definition.scala
    #	src/main/scala/chisel3/util/AttributeAnnotation.scala
    #	src/main/scala/chisel3/util/experimental/Inline.scala
    #	src/main/scala/chisel3/util/experimental/LoadMemoryTransform.scala
    #	src/main/scala/circt/OutputDirAnnotation.scala
    #	src/test/scala-2/chiselTests/util/SRAMSpec.scala
    #	src/test/scala/chiselTests/AnnotatingDiamondSpec.scala
    #	src/test/scala/chiselTests/experimental/hierarchy/Annotations.scala
    #	src/test/scala/circtTests/stage/ChiselStageSpec.scala
    
    * Resolve backport conflicts
    
    * Waive false MiMa issues
    
    * Fix ScalaDoc
    
    ---------
    
    Co-authored-by: Jack Koenig <koenig@sifive.com>
    chiselbot and jackkoenig authored Feb 15, 2025
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    8918516 View commit details

Commits on Feb 27, 2025

  1. [testers] Deprecate everything the testers package (backport #4742) (#…

    …4743)
    
    * [testers] Deprecate everything the testers package (#4742)
    
    Deprecate `BasicTester` and `TesterDriver`.  These have been fully
    replaced with ChiselSim.
    
    Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
    (cherry picked from commit 0a0fa80)
    
    # Conflicts:
    #	src/test/scala/chiselTests/TesterDriverSpec.scala
    
    * fixup! [testers] Deprecate everything the testers package (#4742)
    
    * fixup! [testers] Deprecate everything the testers package (#4742)
    
    ---------
    
    Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
    chiselbot and seldridge authored Feb 27, 2025
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    66580c0 View commit details

Commits on Feb 28, 2025

  1. Mass deprecations, to be removed in Chisel 7 (backport #4754) (#4756)

    * Mass deprecations, to be removed in Chisel 7 (#4754)
    
    Mass deprecation of APIs that we would like to delete in Chisel 7.
    
    Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com
    (cherry picked from commit 868c195)
    
    # Conflicts:
    #	firrtl/src/test/scala/firrtlTests/FileUtilsSpec.scala
    #	src/test/scala/chiselTests/Harness.scala
    
    * fixup! Mass deprecations, to be removed in Chisel 7 (#4754)
    
    * fixup! Mass deprecations, to be removed in Chisel 7 (#4754)
    
    ---------
    
    Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
    chiselbot and seldridge authored Feb 28, 2025
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    55dd49d View commit details

Commits on Mar 1, 2025

  1. Refine annotate and Targetable (backport #4698) (#4703)

    * Refine annotate and Targetable (#4698)
    
    Some minor improvements to the user API for annotating with Targetable
    * Support annotating Seq[Targetable] and provide Targetable for AnyTargetable.
    * Add AnyTargetable.apply for simpler manual conversions.
    * Show tests annotating Seq[Targetable] and manual use of AnyTargetable.
    
    (cherry picked from commit e20069e)
    
    * Run formatting
    
    ---------
    
    Co-authored-by: Jack Koenig <koenig@sifive.com>
    chiselbot and jackkoenig authored Mar 1, 2025
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    9d28ac6 View commit details

Commits on Mar 4, 2025

  1. Warn on <literal>.asUInt|.asSInt(_: Int) (#4764) (#4766)

    The user probably forgot .W. Apply the same technique as used for .U|.S.
    
    (cherry picked from commit 811bb46)
    
    Co-authored-by: Jack Koenig <koenig@sifive.com>
    chiselbot and jackkoenig authored Mar 4, 2025
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    c2a612f View commit details

Commits on Mar 7, 2025

  1. Escape special characters in Property String literals (backport #4564) (

    #4565)
    
    * Escape special characters in Property String literals (#4564)
    
    (cherry picked from commit dc39308)
    
    * Tweak change to make it binary compatible
    
    ---------
    
    Co-authored-by: Jack Koenig <koenig@sifive.com>
    mergify[bot] and jackkoenig authored Mar 7, 2025
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    320dfe8 View commit details
  2. Dev/biancolin/fix module choice under di (backport #4569) (#4570)

    * Fix ModuleChoice under D/I (#4569)
    
    * Use FileCheck in ModuleChoice tests; add a test
    * DRY out module definitions in ModuleChoiceSpec
    * Add a ModuleChoice test using Definition
    * Ensure Groups are propagated to parent builder under D/I
    
    (cherry picked from commit 0070570)
    
    # Conflicts:
    #	core/src/main/scala/chisel3/experimental/hierarchy/core/Definition.scala
    
    * Resolve backport conflicts
    
    * Tweak tests back to 6.x-style
    
    ---------
    
    Co-authored-by: David Biancolin <david.biancolin@gmail.com>
    Co-authored-by: Jack Koenig <koenig@sifive.com>
    Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
    3 people authored Mar 7, 2025
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    4c10d0e View commit details
  3. Support boring on original Module after .toInstance call (backport #4602

    ) (#4604)
    
    * Support boring on original Module after .toInstance call (#4602)
    
    (cherry picked from commit 4d162c4)
    
    * Add needed private API and change new test to 6.x-style
    
    ---------
    
    Co-authored-by: Jack Koenig <koenig@sifive.com>
    Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
    mergify[bot] and jackkoenig authored Mar 7, 2025
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    8db8c1e View commit details
Showing with 1,133 additions and 373 deletions.
  1. +3 −1 .github/workflows/release-notes.yml
  2. +3 −1 .github/workflows/scala-cli-example.yml
  3. +14 −3 build.sbt
  4. +7 −0 core/src/main/scala/chisel3/Aggregate.scala
  5. +52 −6 core/src/main/scala/chisel3/Annotation.scala
  6. +9 −0 core/src/main/scala/chisel3/ChiselEnum.scala
  7. +112 −0 core/src/main/scala/chisel3/ElaboratedCircuit.scala
  8. +6 −0 core/src/main/scala/chisel3/Module.scala
  9. +2 −3 core/src/main/scala/chisel3/dontTouch.scala
  10. +8 −0 core/src/main/scala/chisel3/experimental/EnumAnnotations.scala
  11. +144 −0 core/src/main/scala/chisel3/experimental/Targetable.scala
  12. +2 −6 core/src/main/scala/chisel3/experimental/Trace.scala
  13. +4 −2 core/src/main/scala/chisel3/experimental/hierarchy/core/Definition.scala
  14. +1 −1 core/src/main/scala/chisel3/experimental/hierarchy/core/Lookupable.scala
  15. +8 −7 core/src/main/scala/chisel3/internal/Builder.scala
  16. +2 −0 core/src/main/scala/chisel3/internal/firrtl/IR.scala
  17. +1 −2 core/src/main/scala/chisel3/internal/package.scala
  18. +1 −4 core/src/main/scala/chisel3/package.scala
  19. +1 −1 core/src/main/scala/chisel3/properties/Property.scala
  20. +26 −29 docs/src/cookbooks/hierarchy.md
  21. +1 −6 docs/src/explanations/chisel-type-vs-scala-type.md
  22. +1 −0 firrtl/src/main/scala/firrtl/FileUtils.scala
  23. +1 −1 firrtl/src/main/scala/firrtl/ir/Serializer.scala
  24. +5 −0 firrtl/src/main/scala/firrtl/transforms/BlackBoxSourceHelper.scala
  25. +15 −0 firrtl/src/main/scala/firrtl/util/BackendCompilationUtilities.scala
  26. +2 −0 firrtl/src/test/scala/firrtlTests/FileUtilsSpec.scala
  27. +3 −3 macros/src/main/scala/chisel3/internal/sourceinfo/SourceInfoTransform.scala
  28. +1 −0 project/previous-versions.txt
  29. +4 −4 src/main/scala/chisel3/aop/injecting/InjectingAspect.scala
  30. +104 −21 src/main/scala/chisel3/stage/ChiselAnnotations.scala
  31. +13 −6 src/main/scala/chisel3/stage/ChiselOptions.scala
  32. +4 −3 src/main/scala/chisel3/stage/package.scala
  33. +2 −2 src/main/scala/chisel3/stage/phases/AddDedupGroupAnnotations.scala
  34. +1 −1 src/main/scala/chisel3/stage/phases/AddImplicitOutputAnnotationFile.scala
  35. +1 −1 src/main/scala/chisel3/stage/phases/AddImplicitOutputFile.scala
  36. +2 −2 src/main/scala/chisel3/stage/phases/AddSerializationAnnotations.scala
  37. +2 −6 src/main/scala/chisel3/stage/phases/Convert.scala
  38. +3 −2 src/main/scala/chisel3/stage/phases/Elaborate.scala
  39. +1 −1 src/main/scala/chisel3/stage/phases/Emitter.scala
  40. +1 −0 src/main/scala/chisel3/testers/BasicTester.scala
  41. +6 −2 src/main/scala/chisel3/testers/TesterDriver.scala
  42. +3 −12 src/main/scala/chisel3/util/BlackBoxUtils.scala
  43. +3 −12 src/main/scala/chisel3/util/ExtModuleUtils.scala
  44. +2 −12 src/main/scala/chisel3/util/experimental/ForceNames.scala
  45. +2 −18 src/main/scala/chisel3/util/experimental/Inline.scala
  46. +11 −28 src/main/scala/chisel3/util/experimental/LoadMemoryTransform.scala
  47. +1 −5 src/main/scala/chisel3/util/experimental/decode/decoder.scala
  48. +1 −1 src/main/scala/chisel3/util/random/FibonacciLFSR.scala
  49. +1 −3 src/main/scala/circt/Convention.scala
  50. +4 −4 src/main/scala/circt/stage/ChiselStage.scala
  51. +87 −0 src/test/scala/chisel3/internal/ContainsProbeSpec.scala
  52. +5 −3 src/test/scala/chisel3/stage/ChiselOptionsViewSpec.scala
  53. +4 −9 src/test/scala/chiselTests/AnnotatingDiamondSpec.scala
  54. +30 −5 src/test/scala/chiselTests/BoringUtilsSpec.scala
  55. +3 −0 src/test/scala/chiselTests/ChiselEnum.scala
  56. +9 −0 src/test/scala/chiselTests/Harness.scala
  57. +65 −51 src/test/scala/chiselTests/ModuleChoiceSpec.scala
  58. +39 −11 src/test/scala/chiselTests/NewAnnotationsSpec.scala
  59. +5 −1 src/test/scala/chiselTests/TesterDriverSpec.scala
  60. +5 −10 src/test/scala/chiselTests/experimental/DataViewTargetSpec.scala
  61. +7 −23 src/test/scala/chiselTests/experimental/hierarchy/Annotations.scala
  62. +3 −1 src/test/scala/chiselTests/experimental/hierarchy/SeparateElaborationSpec.scala
  63. +25 −0 src/test/scala/chiselTests/properties/PropertySpec.scala
  64. +2 −2 src/test/scala/chiselTests/stage/phases/AddSerializationAnnotationsSpec.scala
  65. +1 −6 src/test/scala/chiselTests/stage/phases/ConvertSpec.scala
  66. +1 −1 src/test/scala/chiselTests/stage/phases/ElaborateSpec.scala
  67. +3 −7 src/test/scala/chiselTests/util/SRAMSpec.scala
  68. +4 −6 src/test/scala/circtTests/stage/ChiselStageSpec.scala
  69. +32 −15 svsim/src/main/resources/simulation-driver.cpp
  70. +37 −0 svsim/src/test/resources/SIntTest.sv
  71. +89 −0 svsim/src/test/scala/BackendSpec.scala
  72. +70 −0 svsim/src/test/scala/Resources.scala
4 changes: 3 additions & 1 deletion .github/workflows/release-notes.yml
Original file line number Diff line number Diff line change
@@ -19,6 +19,8 @@ jobs:
generate_release_notes:
name: Generate Release Notes
runs-on: ubuntu-22.04
permissions:
contents: write

steps:
- name: Checkout
@@ -41,7 +43,7 @@ jobs:
run: echo "$CHANGELOG" >> $GITHUB_STEP_SUMMARY
- name: Upload Release Notes (on release)
if: github.event_name == 'release'
uses: softprops/action-gh-release@v2.0.5
uses: softprops/action-gh-release@v2.1.0
with:
body: ${{ steps.release-notes.outputs.changelog }}
- name: Error on uncategorized PRs
4 changes: 3 additions & 1 deletion .github/workflows/scala-cli-example.yml
Original file line number Diff line number Diff line change
@@ -14,6 +14,8 @@ jobs:
name: Generate Chisel Scala CLI Example
needs: [generate_scala_cli_example]
runs-on: ubuntu-22.04
permissions:
contents: write

steps:
- name: Download Generated CLI Example
@@ -27,6 +29,6 @@ jobs:
echo '```' >> $GITHUB_STEP_SUMMARY
- name: Upload To Release Page
if: github.event_name == 'release'
uses: softprops/action-gh-release@v2.0.5
uses: softprops/action-gh-release@v2.1.0
with:
files: chisel-example.scala
17 changes: 14 additions & 3 deletions build.sbt
Original file line number Diff line number Diff line change
@@ -77,7 +77,12 @@ lazy val warningSuppression = Seq(
"cat=deprecation&origin=chisel3\\.aop\\.Aspect:s",
"cat=deprecation&origin=chisel3\\.aop\\.Aspect$:s",
"cat=deprecation&origin=chisel3\\.stage\\.phases.AspectPhase:s",
"cat=deprecation&origin=chisel3\\.stage\\.phases.MaybeAspectPhase:s"
"cat=deprecation&origin=chisel3\\.stage\\.phases.MaybeAspectPhase:s",
"cat=deprecation&origin=chisel3\\.InstanceId:s",
"cat=deprecation&origin=chisel3\\.testers\\.BasicTester:s",
"cat=deprecation&origin=chisel3\\.testers\\.TesterDriver:s",
"cat=deprecation&origin=firrtl\\.util\\.BackendCompilationUtilities.*:s",
"cat=deprecation&origin=firrtl\\.transforms\\.BlackBoxSourceHelper.*:s"
).mkString(",")
)

@@ -242,7 +247,8 @@ lazy val pluginScalaVersions = Seq(
"2.13.12",
"2.13.13",
"2.13.14",
"2.13.15"
"2.13.15",
"2.13.16"
)

lazy val plugin = (project in file("plugin"))
@@ -406,7 +412,12 @@ lazy val unipublish =
ProblemFilters.exclude[DirectMissingMethodProblem]("chisel3.*._circuit"),
ProblemFilters.exclude[DirectMissingMethodProblem]("chisel3.*._circuit_="),
// setRef was package private
ProblemFilters.exclude[IncompatibleMethTypeProblem]("chisel3.*.setRef")
ProblemFilters.exclude[IncompatibleMethTypeProblem]("chisel3.*.setRef"),
// ChiselOptions constructor is package private
ProblemFilters.exclude[DirectMissingMethodProblem]("chisel3.stage.ChiselOptions.this"),
// ChiselLoadMemoryAnnotation was private
ProblemFilters.exclude[MissingClassProblem]("chisel3.util.experimental.ChiselLoadMemoryAnnotation"),
ProblemFilters.exclude[MissingClassProblem]("chisel3.util.experimental.ChiselLoadMemoryAnnotation$")
),
// Forward doc command to unidoc
Compile / doc := (ScalaUnidoc / doc).value,
7 changes: 7 additions & 0 deletions core/src/main/scala/chisel3/Aggregate.scala
Original file line number Diff line number Diff line change
@@ -83,6 +83,10 @@ sealed abstract class Aggregate extends Data {
*/
def getElements: Seq[Data]

/** Save this result, as it can be very expensive to determine this otherwise */
private[chisel3] lazy val elementsContainProbe: Boolean =
elementsIterator.exists(d => chisel3.internal.containsProbe(d))

/** Similar to [[getElements]] but allows for more optimized use */
private[chisel3] def elementsIterator: Iterator[Data]

@@ -209,6 +213,9 @@ sealed class Vec[T <: Data] private[chisel3] (gen: => T, val length: Int) extend

override def containsAFlipped = sample_element.containsAFlipped

/** Save this result, as it can be very expensive to determine this otherwise */
override private[chisel3] lazy val elementsContainProbe: Boolean = chisel3.internal.containsProbe(sample_element)

private[chisel3] override def bind(target: Binding, parentDirection: SpecifiedDirection): Unit = {
this.maybeAddToParentIds(target)
binding = target
58 changes: 52 additions & 6 deletions core/src/main/scala/chisel3/Annotation.scala
Original file line number Diff line number Diff line change
@@ -3,8 +3,10 @@
package chisel3.experimental

import scala.language.existentials
import scala.annotation.nowarn
import chisel3.internal.Builder
import chisel3.{Data, InstanceId, RawModule}
import chisel3.{Data, HasTarget, InstanceId, RawModule}
import chisel3.experimental.AnyTargetable
import firrtl.annotations._
import firrtl.options.Unserializable
import firrtl.transforms.{DedupGroupAnnotation, NoDedupAnnotation}
@@ -13,6 +15,10 @@ import firrtl.transforms.{DedupGroupAnnotation, NoDedupAnnotation}
*
* Defines a conversion to a corresponding FIRRTL Annotation
*/
@deprecated(
"Avoid custom annotations. If you must use annotations, use annotate.apply method that takes Data",
"Chisel 6.7.0"
)
trait ChiselAnnotation {

/** Conversion to FIRRTL Annotation */
@@ -23,16 +29,56 @@ trait ChiselAnnotation {
*
* Defines a conversion to corresponding FIRRTL Annotation(s)
*/
@deprecated(
"Avoid custom annotations. If you must use annotations, use annotate.apply method that takes Data",
"Chisel 6.7.0"
)
trait ChiselMultiAnnotation {
def toFirrtl: Seq[Annotation]
}

@nowarn("msg=Avoid custom annotations")
object annotate {
def apply(anno: ChiselAnnotation): Unit = {
@deprecated(
"Avoid custom annotations. If you must use annotations, use annotate.apply method that takes Data",
"Chisel 6.7.0"
)
def apply(anno: ChiselAnnotation): Unit =
Builder.annotations += anno
}
def apply(annos: ChiselMultiAnnotation): Unit = {

@deprecated(
"Avoid custom annotations. If you must use annotations, use annotate.apply method that takes Data",
"Chisel 6.7.0"
)
def apply(annos: ChiselMultiAnnotation): Unit =
Builder.newAnnotations += annos

/** Create annotations.
*
* Avoid this API if possible.
*
* Anything being annotated must be passed as arguments so that Chisel can do safety checks.
* The caller is still responsible for calling .toTarget on those arguments in mkAnnos.
*/
def apply(targets: AnyTargetable*)(mkAnnos: => Seq[Annotation]): Unit = {
targets.map(_.a).foreach {
case d: Data => requireIsAnnotatable(d, "Data marked with annotation")
case _ => ()
}
Builder.newAnnotations += new ChiselMultiAnnotation {
def toFirrtl: Seq[Annotation] = mkAnnos
}
}

/** Create annotations.
*
* Avoid this API if possible.
*
* Anything being annotated must be passed as arguments so that Chisel can do safety checks.
* The caller is still responsible for calling .toTarget on those arguments in mkAnnos.
*/
def apply[T: Targetable](targets: Seq[T])(mkAnnos: => Seq[Annotation]): Unit = {
annotate(targets.map(t => AnyTargetable.toAnyTargetable(t)): _*)(mkAnnos)
}
}

@@ -76,7 +122,7 @@ object doNotDedup {
* @return Unmodified signal `module`
*/
def apply[T <: RawModule](module: T): Unit = {
annotate(new ChiselAnnotation { def toFirrtl = NoDedupAnnotation(module.toNamed) })
annotate(module)(Seq(NoDedupAnnotation(module.toNamed)))
}
}

@@ -89,6 +135,6 @@ object dedupGroup {
* @return Unmodified signal `module`
*/
def apply[T <: BaseModule](module: T, group: String): Unit = {
annotate(new ChiselAnnotation { def toFirrtl = DedupGroupAnnotation(module.toTarget, group) })
annotate(module)(Seq(DedupGroupAnnotation(module.toTarget, group)))
}
}
9 changes: 9 additions & 0 deletions core/src/main/scala/chisel3/ChiselEnum.scala
Original file line number Diff line number Diff line change
@@ -5,6 +5,7 @@ package chisel3
import scala.language.experimental.macros
import scala.language.existentials
import scala.reflect.macros.blackbox.Context
import scala.annotation.nowarn
import scala.collection.mutable
import chisel3.experimental.{annotate, requireIsHardware, ChiselAnnotation, SourceInfo, UnlocatableSourceInfo}
import chisel3.internal.Builder.pushOp
@@ -25,6 +26,9 @@ import chisel3.internal.{

import chisel3.experimental.EnumAnnotations._

// Rather than refactoring the annotation work here, we should just remove ChiselEnum annotations
@nowarn("msg=Avoid custom annotations")
@nowarn("msg=Enum annotations will be removed")
abstract class EnumType(private[chisel3] val factory: ChiselEnum, selfAnnotating: Boolean = true) extends Element {

// Use getSimpleName instead of enumTypeName because for debugging purposes
@@ -228,10 +232,15 @@ abstract class EnumType(private[chisel3] val factory: ChiselEnum, selfAnnotating
}
}

// Rather than refactoring the annotation work here, we should just remove ChiselEnum annotations
@nowarn("msg=Avoid custom annotations")
private[chisel3] object ChiselEnum {
private[chisel3] case object CacheKey extends BuilderContextCache.Key[mutable.HashSet[ChiselAnnotation]]
}

// Rather than refactoring the annotation work here, we should just remove ChiselEnum annotations
@nowarn("msg=Avoid custom annotations")
@nowarn("msg=Enum annotations will be removed")
abstract class ChiselEnum {
class Type extends EnumType(this)
object Type {
112 changes: 112 additions & 0 deletions core/src/main/scala/chisel3/ElaboratedCircuit.scala
Original file line number Diff line number Diff line change
@@ -0,0 +1,112 @@
// SPDX-License-Identifier: Apache-2.0

package chisel3

import firrtl.annotations.Annotation
import firrtl.ir.{CircuitWithAnnos, Serializer}
import firrtl.options.{CustomFileEmission, Unserializable}
import chisel3.experimental.{BaseModule, SourceInfo, UnlocatableSourceInfo}
import chisel3.experimental.hierarchy.Definition
import chisel3.internal.firrtl.ir.Circuit
import chisel3.internal.firrtl.Converter

/** The result of running Chisel elaboration
*
* Provides limited APIs for inspection of the resulting circuit.
*/
// This is an important interface so let's keep it separate from the implementation.
sealed trait ElaboratedCircuit {

/** The name of the circuit, also the name of the top public module */
def name: String

/** The circuit and annotations as a string of FIRRTL IR
*
* This will include annotations passed to Chisel to build the circuit and those created during elaboration.
* For large circuits (> 2 GiB of text) use `lazilySerialize`.
*/
def serialize: String

/** The circuit and annotations as a string of FIRRTL IR
*
* For large circuits (> 2 GiB of text) use `lazilySerialize`.
*
* @param annotations annotations to include in the FIRRTL IR. No other annotations will be included.
*/
def serialize(annotations: Iterable[Annotation]): String

/** The circuit and annotations as a lazy buffer of strings of FIRRTL IR
*
* This will include annotations passed to Chisel to build the circuit and those created during elaboration.
* Serialized lazily to reduce peak memory use and support cicuits larger than 2 GiB.
*/
def lazilySerialize: Iterable[String]

/** The circuit and annotations as a lazy buffer of strings of FIRRTL IR
*
* Serialized lazily to reduce peak memory use and support cicuits larger than 2 GiB.
*
* @param annotations annotations to include in the FIRRTL IR. No other annotations will be included.
*/
def lazilySerialize(annotations: Iterable[Annotation]): Iterable[String]

/** The annotations created during elaboration of this circuit
*
* This does not include annotations passed to elaboration.
*/
def annotations: Iterable[Annotation]

/** The Definition of the top module in the elaborated circuit */
def topDefinition: Definition[BaseModule]

/** The underlying circuit, for private use only */
private[chisel3] def _circuit: Circuit
}

private class ElaboratedCircuitImpl(circuit: Circuit, initialAnnotations: Seq[Annotation]) extends ElaboratedCircuit {

// Source locator needed for toDefinition
private implicit def sourceInfo: SourceInfo = UnlocatableSourceInfo

override def name: String = circuit.name

override def serialize: String = lazilySerialize.mkString

override def serialize(annotations: Iterable[Annotation]): String = lazilySerialize(annotations).mkString

override def lazilySerialize: Iterable[String] = {
val annotations = (initialAnnotations.view ++ circuit.firrtlAnnotations).flatMap {
case _: Unserializable => None
case _: CustomFileEmission => None
case a => Some(a)
}.toVector
lazilySerialize(annotations)
}

override def lazilySerialize(annotations: Iterable[Annotation]): Iterable[String] = {
val prelude = {
val dummyCircuit = circuit.copy(components = Nil)
val converted = Converter.convert(dummyCircuit)
val withAnnos = CircuitWithAnnos(converted, annotations.toVector)
Serializer.lazily(withAnnos)
}
val typeAliases: Seq[String] = circuit.typeAliases.map(_.name)
val modules = circuit.components.iterator.map(c => Converter.convert(c, typeAliases))
val moduleStrings = modules.flatMap { m =>
Serializer.lazily(m, 1) ++ Seq("\n\n")
}
prelude ++ moduleStrings
}

override def annotations: Iterable[Annotation] = circuit.firrtlAnnotations

// TODO come up with a better way to figure this out than "last"
override def topDefinition: Definition[BaseModule] = circuit.components.last.id.toDefinition

private[chisel3] override def _circuit: Circuit = circuit
}

object ElaboratedCircuit {
private[chisel3] def apply(circuit: Circuit, initialAnnotations: Seq[Annotation]): ElaboratedCircuit =
new ElaboratedCircuitImpl(circuit, initialAnnotations)
}
6 changes: 6 additions & 0 deletions core/src/main/scala/chisel3/Module.scala
Original file line number Diff line number Diff line change
@@ -578,6 +578,12 @@ package experimental {
_ports.toSeq
}

/** Get IOs that are currently bound to this module.
*/
private[chisel3] def getIOs: Seq[Data] = {
_ports.map(_._1).toSeq
}

// These methods allow checking some properties of ports before the module is closed,
// mainly for compatibility purposes.
protected def portsContains(elem: Data): Boolean = {
5 changes: 2 additions & 3 deletions core/src/main/scala/chisel3/dontTouch.scala
Original file line number Diff line number Diff line change
@@ -38,9 +38,8 @@ object dontTouch {
data match {
case d if DataMirror.hasProbeTypeModifier(d) => ()
case _: Property[_] => ()
case agg: Aggregate => agg.getElements.foreach(dontTouch.apply)
case _: Element =>
annotate(new ChiselAnnotation { def toFirrtl = DontTouchAnnotation(data.toNamed) })
case agg: Aggregate => agg.getElements.foreach(dontTouch.apply)
case _: Element => annotate(data)(Seq(DontTouchAnnotation(data.toNamed)))
case _ => throw new ChiselException("Non-hardware dontTouch")
}
data
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