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Cranelift: Simple multiplication + out of bounds shift panics with "should be implemented in ISLE: inst = v12 = smulhi.i8 v0, v0, type = Some(types::I8)" #7865

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bjorn3 opened this issue Feb 3, 2024 · 0 comments · Fixed by #7866
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Cranelift: Simple multiplication + out of bounds shift panics with "should be implemented in ISLE: inst = v12 = smulhi.i8 v0, v0, type = Some(types::I8)" #7865

bjorn3 opened this issue Feb 3, 2024 · 0 comments · Fixed by #7866
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bug Incorrect behavior in the current implementation that needs fixing cranelift Issues related to the Cranelift code generator

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@bjorn3
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bjorn3 commented Feb 3, 2024

.clif Test Case

test compile
set opt_level=speed
target x86_64

function u0:9(i8) -> i16 system_v {
block0(v0: i8):
    v8 = sextend.i16 v0
    v9 = imul v8, v8
    v10 = iconst.i64 1000
    v13 = sshr v9, v10  ; v10 = 1000
    return v13
}

Steps to Reproduce

  • Compile the above test case.

Expected Results

Compiles fine and masks the shift amount as expected.

Actual Results

Panics with "should be implemented in ISLE: inst = v12 = smulhi.i8 v0, v0, type = Some(types::I8)"

Versions and Environment

Cranelift version or commit: Tested with 0.104 and b6a8abc.

Operating system: N/A

Architecture: x86_64

Extra Info

Reported to cg_clif by @cbeuw in rust-lang/rustc_codegen_cranelift#1455.
@bjorn3 bjorn3 added bug Incorrect behavior in the current implementation that needs fixing cranelift Issues related to the Cranelift code generator labels Feb 3, 2024
@bjorn3 bjorn3 mentioned this issue Feb 3, 2024
Open
@afonso360 afonso360 mentioned this issue Feb 3, 2024
Merged
alexcrichton added a commit to alexcrichton/wasmtime that referenced this issue Feb 3, 2024
@alexcrichton
x64: Refactor multiplication instructions
c9ce03f 
This commit is inspired after reading over some code from bytecodealliance#7865
and bytecodealliance#7866. The goal of this commit was to refactor
scalar multiplication-related instructions in the x64 backend to more
closely align with their native instructions. Changes include:

* The `MulHi` instruction is renamed to `Mul`. This represents either
  `mul` or `imul` producing a doublewide result.
* A `Mul8` instruction was added to correspond to `Mul` for the 8-bit
  variants that produce a doublewide result in the `AX` register rather
  than the other instructions which split between `RAX` and `RDX`.
* The `UMulLo` instruction was removed as now it's covered by `Mul`
* The `AluRmiROpcode::Mul` opcode was removed in favor of new `IMul` and
  `IMulImm` instructions. Register allocation and emission already had
  special cases for `Mul` which felt better as standalone instructions
  rather than putting in an existing variant.

Lowerings using `imul` are not affected in general but the `IMulImm`
instruction has different register allocation behavior than before which
allows the destination to have a different register than the first
operand. The `umulhi` and `smulhi` instructions are also reimplemented
with their 8-bit variants instead of extension-plus-16-bit variants.
@alexcrichton alexcrichton mentioned this issue Feb 5, 2024
Merged
github-merge-queue bot pushed a commit that referenced this issue Feb 9, 2024
@alexcrichton
x64: Refactor multiplication instructions (#7871)
1f6e901 
* x64: Refactor multiplication instructions

This commit is inspired after reading over some code from #7865
and #7866. The goal of this commit was to refactor
scalar multiplication-related instructions in the x64 backend to more
closely align with their native instructions. Changes include:

* The `MulHi` instruction is renamed to `Mul`. This represents either
  `mul` or `imul` producing a doublewide result.
* A `Mul8` instruction was added to correspond to `Mul` for the 8-bit
  variants that produce a doublewide result in the `AX` register rather
  than the other instructions which split between `RAX` and `RDX`.
* The `UMulLo` instruction was removed as now it's covered by `Mul`
* The `AluRmiROpcode::Mul` opcode was removed in favor of new `IMul` and
  `IMulImm` instructions. Register allocation and emission already had
  special cases for `Mul` which felt better as standalone instructions
  rather than putting in an existing variant.

Lowerings using `imul` are not affected in general but the `IMulImm`
instruction has different register allocation behavior than before which
allows the destination to have a different register than the first
operand. The `umulhi` and `smulhi` instructions are also reimplemented
with their 8-bit variants instead of extension-plus-16-bit variants.

* Remove outdated emit tests

These are all covered by the filetests framework now too.

* Fix Winch build
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x64: Add {u,s}mulhi.i8 instruction support afonso360/wasmtime
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